Integrated circuit chip, integrated circuit package and display apparatus including the integrated circuit chip

An integrated circuit chip comprising:

• a semiconductor on insulator (SOI) substrate comprising a semiconductor body layer having an active surface, a buried insulating film contacting with an opposite surface of the active surface of the semiconductor body layer, and a bulk substrate facing the semiconductor body layer with the buried insulating film therebetween;
• a conductive ion implantation region formed in the bulk substrate at a position adjacent to the buried insulating film;
• a front-end-of-line (FEOL) structure including an integrated circuit portion formed on the active surface of the semiconductor body layer;
• and
• a penetrating electrode portion in a through-via hole penetrating the FEOL structure, the semiconductor body layer, and the buried insulating film in a vertical direction, the penetrating electrode portion having a first end contacting with the conductive ion implantation region, and the penetrating electrode portion defining an inner insulating space inside the through-via hole.

An integrated circuit chip comprising:

• a semiconductor on insulator (SOI) substrate having a structure in which a bulk substrate, a buried insulating film, and a semiconductor body layer are sequentially stacked;
• at least one conductive ion implantation region formed at a position adjacent to the buried insulating film in the bulk substrate;
• a front-end-of-line (FEOL) structure formed on the SOI substrate and comprising an integrated circuit portion formed on an active surface of the semiconductor body layer;
• an electromagnetic shielding structure comprising at least one penetrating electrode portion arranged in at least one through-via hole vertically penetrating the FEOL structure, the semiconductor body layer, and the buried insulating film, the at least one penetrating electrode portion having a first end connected to the at least one conductive ion implantation region and a second end protruding from the semiconductor body layer vertically farther than an upper surface of the FEOL structure, and the at least one penetrating electrode portion defining at least one inner insulating space inside the at least one through-via hole;
• and
• at least one connection terminal configured to be electrically connected to the second end of the at least one penetrating electrode portion.