US 2022/0093513 A1Published application

Method of forming power grid structures

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsHiranmay BISWAS, Chi-Yeh YU, Kuo-Nan YANG, Chung-Hsing WANG, Stefan RUSU, Chin-Shen LIN

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Abstract

A method of forming an IC structure includes forming first and second power rails at a power rail level. First metal segments are formed at a first metal level above the power rail level. Each first metal segment of the plurality of first metal segments overlap one or both of the first power rail or the second power rail. First vias are formed between the power rail level and the first metal level. Second metal segments are formed at a second metal level above the first metal level. At least one second metal segment of the plurality of second metal segments overlaps the first power rail. At least one second metal segment of the plurality of second metal segments overlaps the second power rail. A plurality of second vias are formed between the first metal level and the second metal level.

Claims20

Dependent claims

A method of forming an integrated circuit (IC) structure, the method comprising:

forming a first power rail and a second power rail at a power rail level, the first power rail and the second power rail being oriented in a power rail direction;
forming a plurality of first metal segments at a first metal level above the power rail level, the plurality of first metal segments being oriented in a first metal level direction perpendicular to the power rail direction, each first metal segment of the plurality of first metal segments overlapping one or both of the first power rail or the second power rail;
forming a plurality of first vias between the power rail level and the first metal level, each first via of the plurality of first vias being positioned at a location where a corresponding first metal segment of the plurality of first metal segments overlaps the first power rail or the second power rail;
forming a plurality of second metal segments at a second metal level above the first metal level, each second metal segment of the plurality of second metal segments being oriented in the power rail direction, at least one second metal segment of the plurality of second metal segments overlapping the first power rail, and at least one second metal segment of the plurality of second metal segments overlapping the second power rail;
forming a plurality of second vias between the first metal level and the second metal level, each second via of the plurality of second vias being positioned at a location above a corresponding first via of the plurality of first vias;
forming a first power strap at a power strap level above the second metal level;
and
forming a second power strap at the power strap level;
wherein:
the forming the IC structure further includes:
configuring the IC structure to electrically connect the first power strap to the first power rail and to electrically connect the second power strap to the second power rail;
the forming the plurality of first metal segments includes:
forming each first metal segment of the plurality of first metal segments having a width corresponding to a predetermined minimum width for the first metal level;
the forming the first power strap includes:
forming the first power strap having a width greater than a predetermined minimum width for the power strap level;
and
the forming the second power strap includes:
forming the second power strap having the width greater than the predetermined minimum width for the power strap level.

15 more elements

A method of forming an integrated circuit (IC) structure, the method comprising:

forming a conductive line structure in the IC structure, the forming the conductive line structure including:
forming first and second sets of long pillars resulting in the following:
members of each of the first and second sets of long pillars having long axes that extend in a first direction;
for each of the first and second sets of long pillars, the members correspondingly thereof being non-overlapping of each other with respect to the first direction;
and
the second sets of long pillars being offset in a second direction relative to the first set of long pillars, the second direction being orthogonal to the first direction;
forming a third set of short pillars resulting in the following:
members of the third set of short pillars being non-overlapping of each other;
the members of the third set of short pillars having long axes that extend in the second direction;
the members of the third set of short pillars being overlapping of corresponding long pillars in the first and second sets of long pillars;
the third set of short pillars being organized into groups, each of the groups having a first quantity of short pillars;
for each of the groups of the third set of short pillars, each member of the group correspondingly overlapping a pair, the pair including one member from each of the first and second sets of long pillars;
each long pillar in each of the first and second sets of long pillars being overlapped by a second quantity of corresponding short pillars in the third set;
and
the first quantity of short pillars being less than the second quantity of corresponding short pillars;
and
forming first vias which electrically connect the members of the third set of short pillars correspondingly with the members of the first and second sets of long pillars resulting in the following:
each short pillar overlaps and is electrically connected between a corresponding one of the pairs;
and
each long pillar in each of the first and second sets of long pillars that is overlapped by the second quantity of corresponding short pillars in the third set being electrically connected to the same.

17 more elements

A method of forming an integrated circuit (IC) structure, the method comprising:

forming a conductive line structure in the IC, the forming the conductive line structure including:
forming line segments resulting in the following:
the line segments being non-overlapping of each other;
the line segments having long axes that extend in a first direction;
and
the line segments being offset in a second direction relative to each other, the second direction being orthogonal to the first direction;
forming long pillars organized into sets resulting in the following:
member long pillars of each set being non-overlapping of each other;
the long pillars having long axes that extend in the second direction;
the long pillars being offset in the first direction relative to each other;
the long pillars being overlapping of corresponding ones of the line segments;
the long pillars being organized into groups;
the groups being offset from each other relative to the first direction;
each of the groups having a same quantity of the long pillars;
for each of the groups, the member long pillars thereof being offset relative to the first direction;
for each of the groups, member long pillars thereof being non-overlapping of each other relative to the first direction;
for each of the groups, the member long pillars thereof having corresponding first ends which are aligned relative the second direction;
and
forming vias which electrically connect the long pillars with corresponding ones of the line segments.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/544,937Filed 8 Dec 2021
Priority: 29 Nov 2016
Published: 24 Mar 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10W 20/427
Characterised by their conductive parts: power or ground buses
H10W 20/056
Of conductive parts of the interconnections: by filling conductive material into holes, grooves or trenches
H10W 20/089
By forming openings in the dielectric parts: using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
H10W 20/42
Characterised by their conductive parts: vias, e.g. via plugs

Family

Application62/427,630Us provisional application · filed 29 Nov 2016
Application15/729,281Division · filed 10 Oct 2017
Application17/544,937Division
US 11,251,124 B2Related patent
US 11,935,833 B2Related patent
US 2018/0151496 A1Published application
US 2022/0093513 A1This patent

From the US filing history. Foreign family members aren’t listed.