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US 2022/0093503 A1Published application
Dual-track bitline scheme for 6t sram cells
AssigneeAdvanced Micro Devices, Inc.
InventorsJohn J. Wuu, Richard T. Schultz
Life of this patent
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Abstract
A layout for a 6T SRAM cell array is disclosed. The layout doubles the number of bits per bit cell in the array by implementing dual pairs of bitlines spanning bit cell columns in the array. Alternating connections (e.g., alternating vias) may be provided for wordline access to the bitlines in the layout. Alternating the connections may reduce RC delay in the layout.
Claims20
An integrated circuit layout, comprising:
- a plurality of bit cells positioned as adjacent columns;
- a first pair of bitlines spanning the bit cells;
- and
- a second pair of bitlines spanning the bit cells;
- wherein the first pair of bitlines and the second pair of bitlines alternate connections to adjacent bit cells.
2 more elements
A system, comprising:
- a memory array, the memory array including:
- a plurality of bit cells positioned as adjacent columns;
- a first pair of bitlines spanning the bit cells;
- and
- a second pair of bitlines spanning the bit cells;
- wherein the first pair of bitlines and the second pair of bitlines alternate connections to adjacent bit cells;
- and
- control logic coupled to the memory array.
5 more elements
A memory device, comprising:
- a plurality of bit cells positioned as adjacent columns;
- a first pair of bitlines spanning the bit cells;
- and
- a second pair of bitlines spanning the bit cells;
- wherein the first pair of bitlines and the second pair of bitlines alternate connections to adjacent bit cells.
2 more elements
Dependencies are inferred from the claim text.