Chip with bifunctional routing and associated method of manufacturing

A method for manufacturing a functional chip from a starting structure comprising a substrate, a layer of oxide referred to as third oxide layer, a semiconductor component formed in the third oxide layer and a second oxide layer on which the third oxide layer rests, the method comprising:

• forming routing tracks on a first face, referred to as rear face, the superconductor routing tracks being in electrical contact with the semiconductor component via superconductor vias already present in the starting structure;
• depositing a layer of oxide on the rear face so as to obtain good planarity;
• bonding the rear face on a silicon handle followed by a turning over of the unit thus formed;
• thinning the substrate;
• creating conductor vias connecting the conductor routing tracks located on the rear face;
• creating conductor tracks at the second face so as to form a first conductor routing level;
• depositing a layer of oxide on the second face, referred to as first oxide layer, so as to obtain good planarity;
• step of bonding the second face on a silicon handle;
• and
• removing the first handle.