Semiconductor device

A semiconductor device comprising:

• a semiconductor layer having a first face and a second face facing the first face;
• a first electrode provided on a side of the first face of the semiconductor layer;
• a second electrode provided on a side of the second face of the semiconductor layer;
• a gate electrode provided on the side of the first face of the semiconductor layer;
• an electrode pad provided on the side of the first face of the semiconductor layer;
• a wiring layer provided on the side of the first face of the semiconductor layer and electrically connected to the gate electrode;
• a first polycrystalline silicon layer provided on the side of the first face of the semiconductor layer, the first polycrystalline silicon layer electrically connected to the electrode pad and the wiring layer, the first polycrystalline silicon layer extending in a first direction parallel to the first face, and the first polycrystalline silicon layer including a first p-type region and a first n-type region;
• a second polycrystalline silicon layer provided on the side of the first face of the semiconductor layer, the second polycrystalline silicon layer electrically connected to the electrode pad and the wiring layer, the second polycrystalline silicon layer extending in the first direction, the second polycrystalline silicon layer including a second n-type region and a second p-type region, and the second polycrystalline silicon layer separated from the first polycrystalline silicon layer;
• and
• an insulating layer provided between the first polycrystalline silicon layer and the electrode pad, the insulating layer provided between the second polycrystalline silicon layer and the electrode pad, the insulating layer provided between the first polycrystalline silicon layer and the wiring layer, the insulating layer provided between the second polycrystalline silicon layer and the wiring layer, and the insulating layer including at least one first opening, the insulating layer including at least one second opening, the insulating layer including at least one third opening, and the insulating layer including at least one fourth opening,
• wherein the electrode pad and the first p-type region are electrically connected via the at least one first opening,
• the wiring layer and the first n-type region are electrically connected via the at least one second opening,
• the electrode pad and the second n-type region are electrically connected via the at least one third opening,
• the wiring layer and the second p-type region are electrically connected via the at least one fourth opening,
• a first distance between a first junction plane of the first p-type region and the first n-type region and the at least one first opening is smaller than a second distance between the first junction plane and the at least one second opening, and
• a third distance between a second junction plane of the second n-type region and the second p-type region and the at least one third opening is smaller than a fourth distance between the second junction plane and the at least one fourth opening.