US 2022/0093474 A1Published application

Extension of nanocomb transistor arrangements to implement gate all around

AssigneeIntel Corporation

InventorsVarun Mishra, Stephen M. Cea, Cory E. Weber, Jack T. Kavalieros, Tahir Ghani

Life of this patent

Estimating the term…

Loading patent…

Abstract

Embodiments of the present disclosure are based on extending a nanocomb transistor architecture to implement gate all around, meaning that a gate enclosure of at least a gate dielectric material, or both a gate dielectric material and a gate electrode material, is provided on all sides of each nanoribbon of a vertical stack of lateral nanoribbons of a nanocomb transistor arrangement. In particular, extension of a nanocomb transistor architecture to implement gate all around, proposed herein, involves use of two dielectric wall materials which are etch-selective with respect to one another, instead of using only a single dielectric wall material used to implement conventional nanocomb transistor arrangements. Nanocomb-based transistor arrangements implementing gate all around as described herein may provide improvements in terms of the short-channel effects of conventional nanocomb transistor arrangements.

Claims20

Dependent claims

A method of fabricating a transistor arrangement, the method comprising:

providing a stack of first and second semiconductor materials over a base;
patterning the stack and the base to form a fin having a width and a length for nanoribbons;
forming a trench opening in the fin, the trench opening extending along the length of the fin;
depositing first and second dielectric wall materials into the trench opening so that the second dielectric wall material is between the stack and the first dielectric wall material;
providing a replacement gate over a portion of the fin;
removing the second semiconductor material not covered by the replacement gate to form a first stack of nanoribbons of the first semiconductor material on one side of the trench opening and to form a second stack of nanoribbons of the first semiconductor material on another side of the trench opening;
removing the second dielectric wall material not covered by the replacement gate;
depositing a spacer material;
forming source and drain (S/D) regions in the first semiconductor material;
and
removing the replacement gate, the second semiconductor material that was covered by the replacement gate, and the second dielectric wall material that was covered by the replacement gate and providing a gate stack.

8 more elements

A transistor arrangement, comprising:

a support structure;
a base, having a first face that is a face opposite the support structure and farthest away from the support structure, a first sidewall substantially perpendicular to the support structure, and a second sidewall opposite the first sidewall;
and
a nanoribbon arrangement over the base, the nanoribbon arrangement including:
a nanoribbon, formed of a first semiconductor material and having a long axis parallel to the support structure, where the base is between the support structure and the nanoribbon, and
a gate dielectric material, wrapping around a portion of the nanoribbon between a first plane and a second plane, where each of the first plane and the second plane is substantially perpendicular to each of the support structure and the long axis of the nanoribbon;
wherein:
the transistor arrangement further includes a trench opening partially filled with a first dielectric wall material and partially filled with a second dielectric wall material, the trench opening extending along the long axis of the nanoribbon,
the second sidewall of the base has a first portion and a second portion, the second portion being between the support structure and the first portion,
the transistor arrangement further includes the gate dielectric material between the first portion of the second sidewall of the base and the first dielectric wall material,
a portion of the second dielectric wall material is between the second portion of the second sidewall of the base and the first dielectric wall material, and
the second dielectric wall material is a material that is etch selective with respect to the first dielectric wall material.

9 more elements

A transistor arrangement, comprising:

a support structure;
a nanoribbon arrangement over the support structure, the nanoribbon arrangement including:
a first semiconductor material, shaped as a nanoribbon having a first face opposite the support structure, a second face opposite the first face, a first sidewall substantially perpendicular to the support structure, and a second sidewall opposite the first sidewall, and
a gate stack over a portion of the nanoribbon, the gate stack comprising:
a gate dielectric material wrapping around a portion of the nanoribbon between a first plane and a second plane, where each of the first plane and the second plane is substantially perpendicular to each of the support structure and a long axis of the nanoribbon, and
a gate electrode material wrapping around the gate dielectric material provided over the first face, the second face, and the first sidewall of the nanoribbon;
and
a first dielectric wall material, shaped as a wall substantially perpendicular to the support structure and extending along the second sidewall of the nanoribbon,
wherein the gate dielectric material provided over the second sidewall of the nanoribbon is between, and in contact with, each of the first semiconductor material of the nanoribbon and the first dielectric wall material.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/030,449Filed 24 Sep 2020
Published: 24 Mar 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification21 codes

B82Y 10/00
Nanotechnology for information processing, storage or transmission
H10D 86/011
Manufacture or treatment: comprising FinFETs
H10B 51/10
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors: characterised by the top-view layout
H10B 51/30
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors: characterised by the memory core region