Electronic systems, fault detecting methods thereof, system on chips, and bus systems

A system-on-chip, comprising:

• an error correction code (ECC) encoder configured to generate encoded data by performing ECC encoding of input data;
• a main intellectual property (IP) configured to receive the encoded data and a first control signal and to output an output data through a first data path based on the encoded data and to output a second control signal through a first control signal path based on the first control signal;
• a first delay circuit configured to generate a third control signal by delaying the first control signal by a particular clock cycle;
• a checker IP configured to output a fourth control signal through a second control signal path based on the third control signal;
• an ECC decoder configured to output a data error detection signal by performing ECC decoding of the output data;
• a second delay circuit configured to generate a fifth control signal by delaying the second control signal by the particular clock cycle;
• and
• a checker circuit configured to detect an error of a control signal by comparing the fourth control signal to the fifth control signal,
• wherein the checker IP further comprises a second data path generated through boundary optimization, after the first data path is duplicated and then all inputs are tied.

A bus system, comprising:

• a first intellectual property (IP) configured to output data and a first control signal;
• a second IP configured to output a second control signal;
• an error correction code (ECC) decoder configured to output a data error detection signal by performing ECC decoding of the output data;
• a delay circuit configured to generate a third control signal by delaying the first control signal by a particular clock cycle;
• and
• a checker circuit configured to detect an error of a control signal by comparing the second control signal to the third control signal.