Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells

Integrated circuitry comprising:

• a three-dimensional (3D) array comprising tiers of electronic components;
• a stair-step structure laterally-adjacent the 3D array, the stair-step structure having steps individually comprising a tread and a riser;
• and
• insulating material atop individual of the treads and aside individual of the risers, the insulating material comprising:
• touching insulative physical objects having void-spaces there-among, the insulative physical objects individually having at least one of a maximum submicron dimension or a minimum submicron dimension;
• and
• solid insulative material in the void-spaces.

A memory array comprising strings of memory cells, comprising:

• laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers in a memory-array region;
• the insulative tiers and the conductive tiers of the laterally-spaced memory blocks extending from the memory-array region into a stair-step region that is adjacent the memory-array region, the insulative tiers and the conductive tiers of the memory blocks in the stair-step region comprising stair-step structures that are laterally-spaced relative one another the stair-step structures individually having steps individually comprising a tread and a riser;
• insulating material atop individual of the treads and aside individual of the risers, the insulating material comprising:
• touching insulative physical objects having void-spaces there-among, the insulative physical objects individually having at least one of a maximum submicron dimension or a minimum submicron dimension;
• and
• solid insulative material in the void-spaces.