3d semiconductor memory device and structure
AssigneeMonolithic 3D Inc.
InventorsZvi Or-Bach, Brian Cronquist, Deepak C. Sekar
Life of this patent
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Abstract
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second level includes an array of memory cells, and where each of the memory cells includes at least one recessed-channel-array-transistor (RCAT).
Claims20
A 3D semiconductor device, the device comprising:
- a first level comprising a first single crystal layer, said first level comprising first transistors,
- wherein said first transistors each comprise a single crystal channel;
- first metal layers interconnecting at least said first transistors;
- and
- a second level comprising a second single crystal layer, said second level comprising second transistors,
- wherein said second level overlays said first level,
- wherein said second level is bonded to said first level,
- wherein said bonded comprises oxide to oxide bonds,
- wherein said second level comprises an array of memory cells, and
- wherein each of said memory cells comprises at least one recessed-channel-array-transistor (RCAT).
A 3D semiconductor device, the device comprising:
- a first level comprising a first single crystal layer, said first level comprising first transistors,
- wherein said first transistors each comprise a single crystal channel;
- first metal layers interconnecting at least said first transistors;
- a second level comprising a second single crystal layer, said second level comprising second transistors,
- wherein said second level overlays said first level,
- wherein said second level is bonded to said first level,
- wherein said bonded comprises oxide to oxide bonds,
- wherein said second level comprises an array of memory cells;
- and
- a refresh control circuit adapted to refresh said array of memory cells.
A 3D semiconductor device, the device comprising:
- a first level comprising a first single crystal layer, said first level comprising first transistors,
- wherein said first transistors each comprise a single crystal channel;
- first metal layers interconnecting at least said first transistors;
- and
- a second level comprising a second single crystal layer, said second level comprising second transistors,
- wherein said second level overlays said first level,
- wherein said second level is bonded to said first level,
- wherein said bonded comprises oxide to oxide bonds, and
- wherein said second level comprises at least four independent arrays of memory cells.
The device according to claim
- wherein each of said memory cells comprise at least one recessed-channel-array-transistor (RCAT).
Dependencies are inferred from the claim text.