Method for manufacturing semiconductor device including air gap

A method for manufacturing a semiconductor device, comprising:

• forming a first impurity region on a substrate and a second impurity region on the substrate;
• recessing the first impurity region to form a contact recess;
• forming a bit line structure extending in the contact recess in one direction, the bit line structure contacting the first impurity region, the bit line structure having a first side wall and a second side wall;
• forming an inner spacer on the first side wall and the second side wall of the bit line structure;
• forming a recess filler in the contact recess;
• forming a sacrificial spacer on the inner spacer and on the recess filler;
• forming an outer spacer on the sacrificial spacer;
• forming a storage node contact contacting the second impurity region, the contacting the second impurity region at an outside of the outer spacer;
• partially removing the sacrificial spacer and the outer spacer, to form an air gap between the outer spacer and the inner spacer;
• forming a landing pad on the storage node contact;
• forming a trench defining the landing pad, the forming the trench exposing an upper surface of the sacrificial spacer;
• and
• forming a pad isolation insulating layer filling the trench,
• wherein the forming the outer spacer comprises
• depositing a seed layer using a first silicon source material,
• supplying a purge gas on the seed layer,
• depositing a protective layer on the seed layer by repeating a first cycle comprising supplying a carbon source material and supplying the first silicon source material, and
• depositing a preliminary main spacer on the protective layer by repeating a second cycle comprising supplying a second silicon source material and supplying a first nitrogen source material.

A method for manufacturing a semiconductor device, comprising:

• forming a first impurity region on a substrate and a second impurity region on the substrate;
• recessing the first impurity region, to form a contact recess;
• forming a bit line structure extending in the contact recess in one direction, the bit line structure contacting the first impurity region, the bit line structure having a first side wall and a second side wall;
• forming an inner spacer on each of the first side wall and the second side wall of the bit line structure;
• forming a recess filler in the contact recess;
• forming a capping spacer on the inner spacer and the recess filler;
• forming a sacrificial spacer on the capping spacer;
• forming a protective spacer on the sacrificial spacer;
• forming a storage node contact contacting the second impurity region at an outside of the main spacer;
• removing the sacrificial spacer, to form an air gap between the capping spacer and the protective spacer;
• forming a landing pad on the storage node contact;
• forming a trench defining the landing pad while exposing an upper surface of the sacrificial spacer;
• and
• forming a pad isolation insulating layer filling the trench,
• wherein the forming the capping spacer comprises depositing a capping layer by repeating a first cycle comprising supplying a first silicon source material, supplying a first base source material, and supplying a nitrogen source material, and
• wherein the forming the protective spacer comprises depositing a protective layer by repeating a second cycle comprising supplying the first silicon source material, supplying a second base source material and supplying the nitrogen source material.