Low power memory state retention regulator

A regulator comprising:

• an error amplifier having a first input coupled to receive a reference voltage and a second input coupled to receive a feedback signal;
• a first transistor having a gate electrode coupled to an output of the error amplifier, a first current electrode coupled to a first voltage supply terminal which provides a first non-zero voltage, and a second current electrode coupled to a control node, wherein the control node provides a control voltage;
• a driver transistor having a first current electrode coupled to the first voltage supply terminal, a gate electrode coupled to the control node, and a second current electrode configured to provide an output voltage of the regulator, wherein the output voltage is configured to power a memory (;
• and
• a replica transistor having a first current electrode coupled to the first voltage supply terminal, a gate electrode coupled to the control node, and a second electrode configured to provide a replica voltage, wherein the replica voltage is configured to power a replica of the memory, in which a first ratio of a size of the replica of the memory to a size of the memory is less than one, and a second ratio of a drive strength of the replica transistor to a drive strength of the driver transistor is less than one;
• wherein the regulator is configured to:
• regulate the replica voltage while using the replica voltage as the feedback signal to the error amplifier for a first time period, and
• in response to entering a state retention mode after the first time period, regulate the output voltage while using the output voltage as the feedback signal to the error amplifier for a second time period.