Adaptive dram (dynamic random access memory) burst length for inline ecc (error checking and correction)
AssigneeIntel Corporation
InventorsPuneet WADHAWAN, Sambaran MITRA
Life of this patent
Estimating the term…
Abstract
In a memory subsystem, the memory device and memory controller can exchange data at either a first burst length or a second burst length longer than the first burst length. The memory subsystem includes a cache or other circuitry to buffer ECC (error checking and correction) bits. The memory controller can generate a data read request to read data from memory and a separate ECC read request to read the ECC bits. The ECC cache can buffer ECC bits for multiple data read requests. The memory controller can dynamically switch the ECC read request between the first burst length and the second burst length based on usage of the ECC cache.
Claims22
A memory controller, comprising:
- a hardware interface to couple with a memory device that has a memory array to store data and to store ECC (error checking and correction) bits for the data, wherein the memory device is to exchange data with the memory controller at either a first burst length or a second burst length longer than the first burst length;
- command logic to generate a data read request to read the data and a separate ECC read request to read the ECC bits;
- and
- circuitry to buffer the ECC bits in response to the ECC read request;
- wherein the command logic is to dynamically switch the ECC read request between the first burst length and the second burst length based on usage of the ECC cache.
A system comprising:
- a memory device having a memory array to store data and to store ECC (error checking and correction) bits for the data;
- and
- a memory controller to exchange data with the memory device at either a first burst length or a second burst length longer than the first burst length, the memory controller including:
- command logic to generate a data read request to read the data and a separate ECC read request to read the ECC bits;
- and
- circuitry to buffer the ECC bits in response to the ECC read request;
- wherein the command logic is to dynamically switch the ECC read request between the first burst length and the second burst length based on usage of the ECC cache.
A method for accessing ECC data, comprising:
- exchanging data between a memory controller and a memory device at either a first burst length or a second burst length longer than the first burst length, wherein the memory device has a memory array to store data and to store ECC (error checking and correction) bits for the data;
- generating a data read request to read the data and a separate ECC read request to read the ECC bits;
- and
- buffering ECC bits read with the ECC read request, to store ECC bits for multiple data read requests;
- dynamically switching the ECC read request between the first burst length and the second burst length based on usage of the ECC cache.
Dependencies are inferred from the claim text.