Memory
AssigneeChangxin Memory Technologies, Inc.
InventorsWeibing SHANG, Hongwen LI, Liang ZHANG, Kangling JI, SUNGSOO CHI, Daoxun WU, Ying WANG
Life of this patent
Estimating the term…
Abstract
A memory is provided. The memory includes banks, each bank includes a U half bank and a V half bank; a first error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of output data of the U half banks and the V half banks; and a second error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of the output data of the U half banks and the V half banks.
Claims19
A memory, comprising banks, each bank comprising a U half bank and a V half bank;
- a first error checking and correcting unit connected with U half banks and V half banks and configured to check and correct errors of output data of the U half banks and the V half banks;
- and
- a second error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of output data of the U half banks and the V half banks.
Dependencies are inferred from the claim text.