Semiconductor memory devices and methods of operating semiconductor memory devices

A method of operating a semiconductor memory device including a memory cell array that includes a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of volatile memory cells, the method comprising:

• selecting a first memory cell row from the plurality of memory cell rows based on refresh row addresses for refreshing the memory cell rows;
• performing, by an error correction code (ECC) circuit, an error detection operation on a plurality of sub-pages in the first memory cell row and counting a number of error occurrences in the first memory cell row;
• determining whether to correct a codeword in which an error is detected based on the number of error occurrences in the first memory cell row;
• and
• writing back the codeword in which the error is detected to the memory cell array with or without correction based on the determining.

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cell rows, each of the plurality of memory cell rows including volatile memory cells;
• an error correction code (ECC) circuit;
• a fault address register;
• a refresh control circuit configured to generate refresh row addresses for refreshing the memory cell rows;
• a scrubbing control circuit configured to generate, based on counting the refresh row addresses, scrubbing addresses for performing a scrubbing operation on a first memory cell row selected from the plurality of memory cell rows;
• and
• a control logic circuit configured to control the ECC circuit and the scrubbing control circuit,
• wherein the control logic circuit is configured to:
• control the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences in the first memory cell row;
• determine, based on the number of error occurrences in the first memory cell row, whether to correct a codeword in which an error is detected;
• store a row address of the first memory cell row in the fault address register as a row fault address in response to the number of error occurrences in the first memory cell row being equal to or greater than a reference value;
• and
• control the ECC circuit to skip an ECC decoding on a memory cell row designated by an access address from an external source when the access address matches the row fault address and when the access address is associated with a read command.