Memory system

A memory system comprising:

• a memory device that includes first and second memory cells, a first word line, and first and second bit lines, the first memory cell and the second memory cell being stacked above a substrate, the first memory cell being provided on a first layer, the second memory cell being provided on a second layer, the first word line being coupled to the first memory cell and the second memory cell, the first bit line being coupled to the first memory cell, and the second bit line being coupled to the second memory cell;
• and
• a memory controller configured to control the memory device, the memory controller including a storage circuit capable of storing a correction value table, the correction value table storing a first correction value of a read voltage associated with the first layer and a second correction voltage of a read voltage associated with the second layer, wherein
• the memory controller is configured to:
• select the first word line and instruct the memory device to perform, with different amounts of shift of read voltages, a read operation multiple times for first-page data which is a set of first-bit data;
• calculate a first shift amount of a read voltage optimized for the first layer and a second shift amount of a read voltage optimized for the second layer based on a plurality of first-page data received from the memory device through the read operation performed multiple times;
• and
• select the first word line and instruct the memory device to read the first-page data using a first read voltage to which the first shift amount is applied and to read the first-page data using a second read voltage to which the second shift amount is applied.