Efuse circuit, method, layout, and structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Sheng CHANG, Yao-Jen YANG
Life of this patent
Estimating the term…
Abstract
An IC structure includes a bit line extending in a first direction, first and second pluralities of FinFETs, and a plurality of eFuses. The FinFETs of the first plurality of FinFETs alternate with the FinFETs of the second plurality of FinFETs along the bit line, each eFuse of the plurality of eFuses includes a conductive segment extending between first and second contact regions, the first contact region is electrically connected to the bit line, and the second contact region is electrically connected to each of an adjacent FinFET of the first plurality of FinFETs and an adjacent FinFET of the second plurality of FinFETs.
Claims20
An integrated circuit (IC) structure comprising:
- a bit line extending in a first direction;
- first and second pluralities of fin field-effect transistors (FinFETs), wherein the FinFETs of the first plurality of FinFETs alternate with the FinFETs of the second plurality of FinFETs along the bit line;
- and
- a plurality of electrical fuses (eFuses), wherein
- each eFuse of the plurality of eFuses comprises a conductive segment extending between first and second contact regions,
- the first contact region is electrically connected to the bit line, and
- the second contact region is electrically connected to each of an adjacent FinFET of the first plurality of FinFETs and an adjacent FinFET of the second plurality of FinFETs.
A method of generating an integrated circuit (IC) layout diagram, the method comprising:
- positioning first and second pluralities of fin field-effect transistors (FinFETs) along a bit line in the IC layout diagram, wherein the FinFETs of the first plurality of FinFETs alternate with the FinFETs of the second plurality of FinFETs along the bit line;
- and
- positioning a plurality of electrical fuses (eFuses) along the bit line in the IC layout diagram, wherein
- each eFuse of the plurality of eFuses comprises a conductive segment extending between first and second contact regions,
- the first contact region is electrically connected to the bit line, and
- the second contact region is electrically connected to each of an adjacent FinFET of the first plurality of FinFETs and an adjacent FinFET of the second plurality of FinFETs.
An integrated circuit (IC) structure comprising:
- a bit line;
- first and second pluralities of fin field-effect transistors (FinFETs), wherein the FinFETs of the first plurality of FinFETs alternate with the FinFETs of the second plurality of FinFETs along the bit line;
- and
- a plurality of electrical fuses (eFuses), wherein
- each eFuse of the plurality of eFuses comprises a conductive segment extending between first and second contact regions,
- the first contact region is electrically connected to the bit line, and
- the second contact region is electrically connected to a first plurality of fin structures of an adjacent FinFET of the first plurality of FinFETs and to a second plurality of fin structures of an adjacent FinFET of the second plurality of FinFETs.
Dependencies are inferred from the claim text.