Memory device and operating method thereof
AssigneeSK hynix Inc.
InventorHyung Jin CHOI
Life of this patent
Estimating the term…
Abstract
A memory device having improved performance includes: a plurality of memory cells programmed to one of a plurality of program states divided based on a threshold voltage; and a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines. Each of the plurality of page buffers includes a latch for storing data sensed from a corresponding bit line among the plurality of bit lines, and discharges the corresponding bit line while performing a latch setting operation including setting data stored in the latch in a verify operation on the plurality of program states.
Claims20
A memory device comprising:
- a plurality of memory cells programmed to one of a plurality of program states divided based on a threshold voltage;
- and
- a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines,
- wherein each of the plurality of page buffers includes a latch configured to store data sensed from a corresponding bit line among the plurality of bit lines, and discharges the corresponding bit line while performing a latch setting operation including setting data stored in the latch in a verify operation on the plurality of program states.
A page buffer coupled to a plurality of memory cells through a bit line, the page buffer comprising:
- a latch configured to store data sensed from the bit line;
- a latch setting circuit configured to perform a latch setting operation which includes setting data stored in the latch in a verify operation on the plurality of memory cells;
- and
- a bit line controller configured to discharge the bit line while the latch setting operation is being performed.
A method for operating a memory device including a plurality of memory cells programmed to one of a plurality of program states divided based on a threshold voltage, the method comprising:
- performing a latch setting operation which includes setting data stored in a latch;
- discharging a bit line connected to the plurality of memory cells while performing the latch setting operation;
- and
- precharging the bit line according to whether the latch setting operation has been completed.
Dependencies are inferred from the claim text.