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US 2022/0093185 A1Published application
Semiconductor memory device
AssigneeKioxia Corporation
InventorsMasato DOME, Kensuke YAMAMOTO, Masaru KOYANAGI, Ryo FUKUDA, Junya MATSUNO, Kenro KUBOTA
Life of this patent
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Abstract
According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.
Claims10
A semiconductor memory device comprising:
- a first circuit unit to which a first voltage and a second voltage different from the first voltage are applied, and which is configured to receive a first signal, and output a second signal predicated on the first signal;
- a second circuit unit to which the first voltage and the second voltage are applied, and which is configured to receive the second signal, and output a third signal predicated on the second signal;
- a driver circuit configured to receive a fourth signal predicated on the third signal and output a fifth signal predicated on the fourth signal;
- an input/output pad configured to externally output the fifth signal;
- a first power supply pad to which the first voltage is supplied from the outside;
- a second power supply pad to which the second voltage is supplied from the outside;
- a first interconnect configured to provide coupling between the first circuit unit and the first power supply pad;
- and
- a second interconnect configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.
6 more elements
A semiconductor memory device comprising:
- a first circuit unit to which a first voltage and a second voltage different from the first voltage are applied, and which is configured to receive a first signal, and output a second signal predicated on the first signal;
- a second circuit unit to which the first voltage and the second voltage are applied, and which is configured to receive the second signal, and output a third signal predicated on the second signal;
- a driver circuit configured to receive a fourth signal predicated on the third signal and output a fifth signal predicated on the fourth signal;
- an input/output pad configured to externally output the fifth signal;
- a first power supply pad to which the first voltage is supplied from the outside;
- a second power supply pad to which the second voltage is supplied from the outside;
- a first interconnect configured to provide coupling between the first circuit unit and the second power supply pad;
- and
- a second interconnect configured to provide coupling between the second circuit unit and the second power supply pad and have no electrical coupling to the first interconnect.
6 more elements
A semiconductor memory device comprising:
- a first circuit unit to which a first voltage and a second voltage different from the first voltage are applied, and which is configured to receive a first signal, and output a second signal predicated on the first signal;
- a second circuit unit to which the first voltage and the second voltage are applied, and which is configured to receive the second signal, and output a third signal predicated on the second signal;
- a driver circuit configured to receive a fourth signal predicated on the third signal and output a fifth signal predicated on the fourth signal;
- an input/output pad configured to externally output the fifth signal;
- a first power supply pad to which the first voltage is supplied from the outside;
- a second power supply pad to which the second voltage is supplied from the outside;
- a first interconnect coupled to the first power supply pad;
- a first transistor in which a first end of a current path is coupled to the first interconnect;
- a second interconnect configured to provide coupling between the first circuit unit and a second end of the current path of the first transistor;
- a second transistor different from the first transistor, in which a first end of a current path is coupled to the first interconnect;
- and
- a third interconnect configured to provide coupling between the second circuit unit and a second end of the current path of the second transistor and have no electrical coupling to the second interconnect.
9 more elements
Dependencies are inferred from the claim text.