Memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsJoonsoo Kwon, Seongjin Kim, Wandong Kim
Life of this patent
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Abstract
A memory device includes a cell region in which memory blocks are disposed, each memory block including word lines stacked on a substrate, and channel structures penetrating through the word lines, and a peripheral circuit region including peripheral circuits executing an erase operation of deleting data for each of the memory blocks as a unit. The peripheral circuits control a voltage applied to each word line included in a target memory block to delete data in the erase operation, based on at least one of a position of the target memory block, a height of each word line included in the target memory block, and a profile of each channel structure.
Claims20
A memory device, comprising:
- a cell region in which a plurality of memory blocks, each of the plurality of memory blocks including a plurality of memory cells, are disposed;
- and
- a peripheral circuit region including peripheral circuits configured to execute an erase operation for each of the plurality of memory blocks as a unit,
- wherein each of the plurality of memory blocks comprises a plurality of word lines stacked on a substrate, a plurality of channel structures extending in a first direction, perpendicular to an upper surface of the substrate, and penetrating through the plurality of word lines, and a source region formed in the substrate and connected to the plurality of channel structures, and
- wherein the peripheral circuits are configured to:
- apply an erase voltage to the source region included in at least one of the plurality of memory blocks,
- change a voltage of a first word line from a first bias voltage to a second bias voltage at a first point in time, the first word line being disposed in one of the at least one of the plurality of memory blocks, and
- change a voltage of a second word line, different from the first word line, from the first bias voltage to the second bias voltage at a second point in time, different from the first point in time, the second word line being disposed in one of the at least one of the plurality of memory blocks.
A memory device, comprising:
- a cell region in which a plurality of memory blocks are disposed, each of the plurality of memory blocks including a plurality of word lines stacked on a substrate, and a plurality of channel structures penetrating through the plurality of word lines;
- and
- a peripheral circuit region including peripheral circuits configured to execute an erase operation of deleting data for each of the plurality of memory blocks as a unit,
- wherein the peripheral circuits are configured to, in the erase operation, control a voltage applied to each of the plurality of word lines included in a target memory block to delete data, among the plurality of memory blocks, based on at least one of a position of the target memory block, a height of each of the plurality of word lines included in the target memory block, and a profile of each of the plurality of channel structures.
A memory device, comprising:
- a first memory plane and a second memory plane, each of the first memory plane and the second memory plane including a first memory block and a second memory block;
- a first peripheral circuit including a first page buffer, a first row decoder, and a first word line voltage generator connected to the first memory plane;
- and
- a second peripheral circuit including a second page buffer, a second row decoder, and a second word line voltage generator connected to the second memory plane,
- wherein each of the first word line voltage generator and the second word line voltage generator is configured to control word line voltages differently in an erase operation for the first memory block and an erase operation for the second memory block.
Dependencies are inferred from the claim text.