Semiconductor storage device

A semiconductor storage device comprising:

• a first memory cell array configured to store user data and system information, which is used for a write operation and a read operation on the user data;
• a plurality of first bit lines;
• a second memory cell array configured to store the user data and the system information;
• a plurality of second bit lines;
• a first latch circuit configured to store first system information which are read from the first memory cell array;
• a second latch circuit configured to store second system information which are read from the second memory cell array;
• and
• a control circuit configured to execute a first process of reading the first system information from the first memory cell array using even-numbered first bit lines and storing the first system information in the first latch circuit during a first time period and a second process of reading the second system information from the second memory cell array using odd-numbered second bit lines and storing the second system information in the second latch circuit during a second time period that overlaps with the first time period.

A semiconductor storage device comprising:

• a first memory cell array configured to store user data and system information, which is used for a write operation and a read operation on the user data;
• a plurality of first bit lines electrically connected to memory cells of the first memory cell array;
• a first sense amplifier circuit connected to the first bit lines and including a first latch circuit configured to store first system information which are read from the first memory cell array and a second latch circuit configured to store second system information which are read from the first memory cell array;
• a second memory cell array configured to store the user data and the system information;
• a plurality of second bit lines electrically connected to memory cells of the second memory cell array;
• a second sense amplifier circuit connected to the second bit lines and including a third latch circuit configured to store third system information which are read from the second memory cell array and a fourth latch circuit configured to store fourth system information which are read from the second memory cell array;
• and
• a control circuit configured to:
• execute in parallel and during a first time period, a first process of reading the first system information from the first memory cell array using even-numbered first bit lines and storing the first system information in the first latch circuit and a second process of reading the third system information from the second memory cell array using odd-numbered second bit lines and storing the third system information in the third latch circuit, and
• execute in parallel and during a second time period that follows the first time period, a third process of reading the second system information from the first memory cell array using odd-numbered first bit lines and storing the second system information in the second latch circuit and a fourth process of reading the fourth system information from the second memory cell array using even-numbered second bit lines and storing the fourth system information in the fourth latch circuit.