Dual-port sram cell and layout structure thereof

A layout structure of a dual-port SRAM cell, comprising:

• an active region pattern layer comprising a first, a second, a third, a fourth, a fifth, and a sixth active region patterns, sequentially arranged at intervals from left to right;
• wherein a first NMOS transistor and a first pull-down transistor share the first active region pattern, a first pull-up transistor is arranged in the second active region pattern, a first PMOS transistor is arranged in the third active region pattern, a second PMOS transistor is arranged in the fourth active region pattern, a second pull-up transistor is arranged in the fifth active region pattern, and wherein a second pull-down transistor and a second NMOS transistor share the sixth active region pattern;
• a polysilicon pattern layer disposed on the active region pattern layer, wherein the polysilicon pattern layer comprises:
• a first polysilicon pattern disposed across the first active region pattern and serving as a gate of the first NMOS transistor;
• a second polysilicon pattern disposed across the first, second, and fourth active region patterns, wherein a portion of the second polysilicon pattern that is disposed across the first active region pattern serves as a gate of the first pull-down transistor, a portion of the second polysilicon pattern that is disposed across the second active region pattern serves as a gate of the first pull-up transistor, and a portion of the second polysilicon pattern that is disposed across the fourth active region pattern serves as a gate of the second PMOS transistor;
• wherein the polysilicon pattern layer further comprises:
• a third polysilicon pattern disposed across the third, the fifth, and the sixth active region patterns;
• and
• a fourth polysilicon pattern disposed across the sixth active region pattern, wherein a portion of the third polysilicon pattern that is disposed across the third active region pattern serves as a gate of the first PMOS transistor, a portion of the third polysilicon pattern that is disposed across the fifth active region pattern serves as a gate of the second pull-up transistor, a portion of the third polysilicon pattern that disposed across the sixth active region pattern serves as a gate of the second pull-down transistor, and the fourth polysilicon pattern that is disposed across the sixth active region pattern serves as a gate of the second NMOS transistor;
• a contact hole pattern layer disposed across the polysilicon pattern layer, wherein the contact hole pattern layer comprises:
• a first contact hole pattern and a second contact hole pattern distributed in the first active region pattern and on upper and lower sides of the first polysilicon pattern, a third contact hole pattern and a fourth contact hole pattern distributed in the first active region pattern and on a lower side of the second polysilicon pattern, a fifth contact hole pattern and a sixth contact hole pattern distributed in the second active region pattern and on upper and lower sides of the second polysilicon pattern, a seventh contact hole pattern and a eighth contact hole pattern distributed in the third active region pattern and on upper and lower sides of the third polysilicon pattern, a ninth contact hole pattern and a tenth contact hole pattern distributed in the fourth active region pattern and on upper and lower sides of the second polysilicon pattern, a eleventh contact hole pattern and a twelfth contact hole pattern distributed in the fifth active region pattern and on upper and lower sides of the third polysilicon pattern, a thirteenth contact hole pattern and a fourteenth contact hole pattern distributed in the sixth active region pattern and on an upper side of the third polysilicon pattern, and a fifteenth contact hole pattern and a sixteenth contact hole pattern distributed in the sixth active region pattern and on upper and lower sides of the fourth polysilicon pattern;
• wherein the contact hole pattern layer further comprises:
• a seventeenth contact hole pattern at one end of the first polysilicon pattern, and an eighteenth contact hole pattern at one end of the fourth polysilicon pattern;
• wherein a first metal layer is disposed on the contact hole pattern layer, wherein the first metal layer comprises:
• a first metal pattern disposed on the seventeenth contact hole pattern, a second metal pattern disposed on the first contact hole pattern, a third metal pattern disposed on the second contact hole pattern and connected to the fifth contact hole pattern, a fourth metal pattern disposed on the third and fourth contact hole patterns, a fifth metal pattern disposed on the sixth contact hole pattern, a sixth metal pattern disposed on the seventh contact hole pattern, a seventh metal pattern disposed on the eighth and ninth contact hole patterns, an eighth metal pattern disposed on the tenth contact hole pattern, a ninth metal pattern disposed on the eleventh contact hole pattern, a tenth metal pattern disposed on the twelfth and fifteenth contact hole patterns, an eleventh metal pattern disposed on the thirteenth and fourteenth contact hole patterns, a twelfth metal pattern disposed on the sixteenth contact hole pattern, and a thirteenth metal pattern disposed on the eighteenth contact hole pattern;
• and
• wherein the first, seventh, and thirteenth metal patterns are connected to a word line, the second metal pattern is connected to a first bit line, the fourth metal pattern and the eleventh metal pattern are grounded, the sixth metal pattern is connected to a second bit line, the eighth metal pattern is connected to a fourth bit line, the fifth metal pattern and the ninth metal pattern are connected to a common power supply of voltage Vdd, and the twelfth metal pattern is connected to a third bit line.