Read refresh operation
AssigneeMicron Technology, Inc.
InventorsFabio Pellizzer, Karthik Sarpatwari, Innocenzo Tortorelli, Nevil N. Gajera
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for read refresh operations are described. A memory device may include a plurality of sub-blocks of memory cells. Each sub-block may undergo a quantity of access operations (e.g., read operations, write operations). Based on the quantity of access operations performed on any one sub-block over a period of time, a read refresh operation may be performed on the memory cells of the sub-block. A read refresh operation may refresh and/or restore the data stored to the memory cells of the sub-block, and be initiated based on the memory device receiving an operation code (e.g., from a host device).
Claims21
(canceled)
A method, comprising:
- applying a first voltage to a memory cell of a sub-block of a memory array as part of a read refresh operation for the sub-block;
- reading a logic state of the memory cell based at least in part on applying the first voltage, wherein reading the logic state of the memory cell comprises detecting whether a first snapback event associated with the memory cell occurs;
- and
- applying, to the memory cell, one or more additional voltages as part of the read refresh operation based at least in part on detecting whether the first snapback event occurs.
An apparatus, comprising:
- a memory array;
- and
- a controller coupled with the memory array, wherein the controller is configured to cause the apparatus to:
- apply a first voltage to a memory cell of a sub-block of the memory array as part of a read refresh operation for the sub-block;
- read a logic state of the memory cell based at least in part on applying the first voltage, wherein reading the logic state of the memory cell comprises detecting whether a first snapback event associated with the memory cell occurs;
- and
- apply, to the memory cell, one or more additional voltages as part of the read refresh operation based at least in part on detecting whether the first snapback event occurs.
A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to:
- apply a first voltage to a memory cell of a sub-block of a memory array of the electronic device as part of a read refresh operation for the sub-block;
- read a logic state of the memory cell based at least in part on applying the first voltage, wherein reading the logic state of the memory cell comprises detecting whether a first snapback event associated with the memory cell occurs;
- and
- apply, to the memory cell, one or more additional voltages as part of the read refresh operation based at least in part on detecting whether the first snapback event occurs.
Dependencies are inferred from the claim text.