US 2022/0093162 A1Published application

Arithmetic device and arithmetic method

AssigneeKioxia Corporation

InventorFumihiko TACHIBANA

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Abstract

According to one embodiment, an arithmetic device includes a first memory cell, a first bit line, a first transistor, a second memory cell, a second bit line, a second transistor, a third bit line, a first switching circuit, a second switching circuit and a controller. The controller sets a conduction state between the first memory cell and the first bit line by the first transistor, and sets a conduction state between the second memory cell and the second bit line by the second transistor. The controller sets the first switching circuit and the second switching circuit in a coupled state and sets the conduction state between the first bit line and the third bit line and between the second bit line and the third bit line to transition voltages of the first, second and third bit lines to a first voltage.

Claims20

Dependent claims

An arithmetic device comprising:

a first memory cell including a first inverter and a second inverter;
a first bit line electrically coupled to the first memory cell;
a first transistor electrically coupled between the first memory cell and the first bit line;
a second memory cell including a third inverter and a fourth inverter;
a second bit line electrically coupled to the second memory cell, the second bit line differing from the first bit line;
a second transistor electrically coupled between the second memory cell and the second bit line;
a third bit line which differs from both the first bit line and the second bit line;
a first switching circuit electrically coupled between the first bit line and the third bit line, the first switching circuit being configured to switch between the first bit line and the third bit line to either a coupled state or a decoupled state;
a second switching circuit electrically coupled between the second bit line and the third bit line, the second switching circuit being configured to switch between the second bit line and the third bit line to either a coupled state or a decoupled state;
and
a controller configured to control the first transistor, the second transistor, the first switching circuit, and the second switching circuit,
wherein the controller is configured to:
set a conduction state between the first memory cell and the first bit line by the first transistor;
set a conduction state between the second memory cell and the second bit line by the second transistor;
set the first switching circuit and the second switching circuit in a coupled state;
and
set the conduction state between the first bit line and the third bit line and between the second bit line and the third bit line to transition voltages of the first bit line, the second bit line, and the third bit line to a first voltage.

14 more elements

An arithmetic method for an arithmetic device including a first memory cell of a static random access memory (SRAM) and a second memory cell of the SRAM, the arithmetic method comprising:

reading data stored in the first memory cell into a first bit line;
reading data stored in the second memory cell into a second bit line, the second bit line differing from the first bit line;
setting a conduction state between the first bit line and a third bit line and a conduction state between the second bit line and the third bit line after reading data into the first bit line and the second bit line, the third bit line differing from the first bit line and the second bit line;
transitioning a voltage of the third bit line to a first voltage by sharing charges of the first bit line, the second bit line, and the third bit line;
converting the first voltage of the third bit line into a first value of a digital value;
calculating a second value by maintaining the first value or subjecting the first value to a bit shift according to weights given to the data in the first and second memory cells;
and
outputting an accumulated value obtained by accumulating the second value.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/353,044Filed 21 Jun 2021
Priority: JP 2020-15832923 Sep 2020
Published: 24 Mar 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G11C 7/1006
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data managing, e.g. manipulating data before…
G11C 11/4094
Read-write [R-W] circuits: bit-line management or control circuits
G11C 5/06
Details of stores covered by group G11C11/00: arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 11/4074
For memory cells of the field-effect type: power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage…