Memory device

A memory device comprising:

• a first conductive layer provided above a substrate in a first direction perpendicular to a surface of the substrate;
• a second conductive layer provided between the first conductive layer and the substrate;
• a third conductive layer provided between the first conductive layer and the second conductive layer;
• a fourth conductive layer provided between the first conductive layer and the third conductive layer;
• a plurality of first pillars extending in the first direction, being adjacent to the first to fourth conductive layers in a second direction parallel to the surface of the substrate, and each including a first ferroelectric layer;
• a plurality of first transistors provided between the first conductive layer and each of the plurality of first pillars;
• a plurality of second transistors provided between the second conductive layer and each of the plurality of first pillars;
• a plurality of first memory cells provided between the third conductive layer and each of the plurality of first pillars;
• a plurality of second memory cells provided between the fourth conductive layer and each of the plurality of first pillars;
• and
• a circuit configured to execute a first operation in which memory cells belonging to one group selected from a first group and a second group are set to a programmed state, the first group including the plurality of first memory cells and the second group including the plurality of second memory cells, a second operation in which memory cells belonging to at least one group selected from the first and second groups are set to an erased state using a first voltage, and a third operation in which a second voltage is applied between each of the plurality of first pillars and one layer among the third and fourth conductive layers, the one layer corresponding to the one group selected from the first and second groups,
• wherein
• each of the plurality of first memory cells includes a first ferroelectric transistor,
• each of the plurality of second memory cells includes a second ferroelectric transistor,
• the first voltage has a first potential difference between each of the plurality of first pillars and at least one layer among the third and fourth layers, the at least one layer corresponding to the at least one group, and a potential of the at least one layer is lower than a potential of the each of the plurality of first pillars,
• the second voltage has a second potential difference between the each of the plurality of first pillars and the one layer, the second potential difference is smaller than the first potential difference, and a potential of the one layer is lower than a potential of the each of the plurality of first pillars, and
• the circuit
• executes, after executing the first operation for the one group, the third operation for the one group, and
• executes the second operation for the at least one group after the third operation.

A memory device comprising:

• a first conductive layer provided above a substrate in a first direction perpendicular to a surface of the substrate;
• a second conductive layer provided between the first conductive layer and the substrate;
• a third conductive layer provided between the first conductive layer and the second conductive layer;
• a fourth conductive layer provided between the first conductive layer and the third conductive layer;
• a plurality of first pillars extending in the first direction, being adjacent to the first to fourth conductive layers in a second direction parallel to the surface of the substrate, and each including a first ferroelectric layer;
• a plurality of first transistors provided between the first conductive layer and each of the plurality of first pillars;
• a plurality of second transistors provided between the second conductive layer and each of the plurality of first pillars;
• a plurality of first memory cells provided between the third conductive layer and each of the plurality of first pillars;
• a plurality of second memory cells provided between the fourth conductive layer and each of the plurality of first pillars;
• and
• a circuit configured to control a first group including the plurality of first memory cells and a second group including the plurality of second memory cells,
• wherein
• each of the plurality of first memory cells includes a first ferroelectric transistor,
• each of the plurality of second memory cells includes a second ferroelectric transistor, and
• the circuit executes an erase operation in which memory cells belonging to one group selected from the first and second groups are set to a erased state.