Semiconductor memory device

A semiconductor memory device comprising

• a first memory transistor, a first memory capacitor, and a control circuit connected to the first memory transistor and the first memory capacitor, wherein
• the first memory transistor includes:
• a first gate electrode;
• a first semiconductor layer opposed to the first gate electrode;
• and
• a first insulating film disposed between the first gate electrode and the first semiconductor layer and containing an insulating material,
• the first memory capacitor includes:
• a first electrode;
• a second electrode opposed to the first electrode;
• and
• a second insulating film disposed between the first electrode and the second electrode, the second insulating film containing the insulating material of the first insulating film,
• the control circuit is configured to perform:
• a first erase operation that supplies the first memory transistor with a first erase voltage;
• a second erase operation that supplies the first memory transistor with a second erase voltage larger than the first erase voltage;
• a first read operation that supplies at least one of the first electrode or the second electrode with a voltage, wherein
• the control circuit performs the first erase operation or the second erase operation after performing the first read operation.

A semiconductor memory device comprising

• a first memory transistor, a second memory transistor, a first memory capacitor, and a control circuit connected to the first memory transistor, the second memory transistor, and the first memory capacitor, wherein
• the first memory transistor includes:
• a first gate electrode;
• a first semiconductor layer opposed to the first gate electrode;
• and
• a first insulating film disposed between the first gate electrode and the first semiconductor layer and containing an insulating material,
• the second memory transistor includes:
• a second gate electrode;
• a second semiconductor layer opposed to the second gate electrode;
• and
• a second insulating film disposed between the second gate electrode and the second semiconductor layer,
• the first memory capacitor includes:
• a first electrode;
• a second electrode opposed to the first electrode;
• and
• a third insulating film disposed between the first electrode and the second electrode, the third insulating film containing the insulating material of the first insulating film,
• the control circuit performs:
• a first read operation that supplies at least one of the first electrode or the second electrode with a voltage;
• a second read operation that supplies the first gate electrode with a read voltage after performing the first read operation;
• a program operation that supplies the second gate electrode with a program voltage larger than the read voltage after performing the second read operation;
• and
• a refresh operation that supplies the first memory transistor with a voltage larger than the program voltage after performing the program operation.