Variable resistance memory device
AssigneeKioxia Corporation
InventorKosuke HATSUDA
Life of this patent
Estimating the term…
Abstract
A first memory cell is coupled to first and third interconnects. A second memory cell is coupled to second. and fourth interconnects first sense amplifier has a first terminal coupled to the first interconnect and a node of a first potential and a second terminal located close to a node of a second potential and coupled to the third interconnect and has a potential difference between the first and second terminals. A second sense amplifier has a third terminal coupled to the fourth interconnect and a node of a third potential and a fourth terminal located close to a node of a fourth potential and coupled to the second interconnect and has a potential difference between the third and fourth terminals.
Claims12
A variable resistance memory device comprising:
- a first interconnect;
- a second interconnect;
- a third interconnect;
- a fourth interconnect;
- a first memory cell coupled to the first interconnect and the third interconnect and having a variable resistance;
- a second memory cell coupled to the second interconnect and the fourth interconnect and having a variable resistance;
- a first sense amplifier having a first terminal and a second terminal and having a potential difference between the first terminal and the second terminal, the first terminal being coupled to the first interconnect and a node of a first potential, and the second terminal being located close to a node of a second potential and coupled to the third interconnect;
- and
- a second sense amplifier having a third terminal and a fourth terminal and having a potential difference between the third terminal and the fourth terminal, the third terminal being coupled to the fourth interconnect and a node of a third potential, and the fourth terminal being located close to a node of a fourth potential and coupled to the second interconnect.
Dependencies are inferred from the claim text.