A display panel, comprising a gate driver circuit, and the gate driver circuit comprising a plurality of cascaded shift registers, wherein each of the plurality of cascaded shift registers comprises an input unit, a node control unit, a first output unit, and a second output unit,
- wherein a first terminal of the input unit is electrically connected to a signal input terminal, a control terminal of the input unit is electrically connected to a first signal terminal, a second terminal of the input unit is electrically connected to a first node, and the input unit is configured to control a voltage of the first node according to a voltage of the first signal terminal and a voltage of the signal input terminal;
- a first terminal of the node control unit is electrically connected to the first node, a second terminal of the node control unit is electrically connected to the first signal terminal, a third terminal of the node control unit is electrically connected to a first power supply voltage terminal, a fourth terminal of the node control unit is electrically connected to a second power supply voltage terminal, a first control terminal of the node control unit is electrically connected to the first node, a second control terminal of the node control unit is electrically connected to a second signal terminal, a fifth terminal of the node control unit is electrically connected to a second node, and the node control unit is configured to control a voltage of the second node according to the voltage of the first node, the voltage of the first signal terminal, a voltage of the first power supply voltage terminal, a voltage of the second power supply voltage terminal, and a voltage of the second signal terminal;
- a first terminal of the first output unit is electrically connected to the second power supply voltage terminal, a second terminal of the first output unit is electrically connected to a third signal terminal, a third terminal of the first output unit is electrically connected to a first output terminal, a first control terminal of the first output unit is electrically connected to the second node, a second control terminal of the first output unit is electrically connected to the first node, and the first output unit is configured to control a voltage of the first output terminal according to the voltage of the second power supply voltage terminal, a voltage of the third signal terminal, the voltage of the first node, and the voltage of the second node;
- and
- a first terminal of the second output unit is electrically connected to the second power supply voltage terminal, a second terminal of the second output unit is electrically connected to a fourth signal terminal, a third terminal of the second output unit is electrically connected to a second output terminal, a first control terminal of the second output unit is electrically connected to the second node, a second control terminal of the second output unit is electrically connected to the first node, and the second output unit is configured to control a voltage of the second output terminal according to the voltage of the second power supply voltage terminal, a voltage of the fourth signal terminal, the voltage of the first node, and the voltage of the second node;
- wherein the display panel further comprising a plurality of pixel driver circuits arranged in an array, and
- wherein each of the plurality of pixel driver circuits comprises a first scanning signal terminal and a second scanning signal terminal, and wherein a first output terminal of a j-th stage shift register is electrically connected to first scanning signal terminals of the plurality of pixel driver circuits in a j-th row, and a second output terminal of the j-th stage shift register is electrically connected to the second scanning signal terminal of each of the plurality of pixel driver circuits in the j-th row, and j is a positive integer greater than or equal to 1;
- or,
- wherein each of the plurality of pixel driver circuits comprises a scanning signal terminal, wherein a first output terminal of a j-th stage shift register is electrically connected to the scanning signal terminal of each of the plurality of pixel driver circuits in a (2j−1)-th row, and a second output terminal of the j-th stage shift register is electrically connected to the scanning signal terminal of each of the plurality of pixel driver circuits in a 2j-th row, and j is a positive integer greater than or equal to 1.