Pixel circuit for controlling junction voltage of light emitting element to be within preset voltage range, display panel and display device

A pixel circuit, comprising a reset subcircuit, a data refreshing subcircuit, a driving subcircuit, a light emission control subcircuit and a potential compensation subcircuit, wherein

• the reset subcircuit is connected with a driving node, and is configured to reset the driving node;
• the data refreshing subcircuit is connected with the driving node, and is configured to store a data voltage and control a voltage of the driving node to be a first voltage;
• the driving subcircuit is connected with the driving node and the light emission control subcircuit, respectively, and is configured to be turned on or off according to the voltage of the driving node;
• the light emission control subcircuit is connected with a light emitting element, and is configured to control a light emission driving voltage to be written in an anode node of the light emitting element via the driving subcircuit and the light emission control subcircuit;
• the potential compensation subcircuit is connected with the light emitting element, and is used for controlling a junction voltage of the light emitting element to be within a preset voltage range according to an initial voltage input by an initialization reset voltage terminal and a reset sequence input by a reset sequence signal terminal, wherein the preset voltage range is higher than zero and lower than an emission threshold voltage of the light emitting element;
• wherein the potential compensation subcircuit is further electrically connected to a preset sequence signal terminal, wherein the preset sequence signal terminal is used for inputting a preset sequence, and the potential compensation subcircuit is used for controlling the junction voltage of the light emitting element to be within the preset voltage range according to the preset sequence, the initial voltage and the reset sequence;
• wherein the preset sequence signal terminal is a compensation and refreshing sequence signal terminal, and the preset sequence is a compensation and refreshing sequence;
• the potential compensation subcircuit comprises a reset transistor, a compensation transistor, and a compensation capacitor, wherein
• a gate of the reset transistor is electrically connected to the reset sequence signal terminal, a first electrode of the reset transistor is electrically connected to the initialization reset voltage terminal, and a second electrode of the reset transistor is electrically connected to a first electrode of the compensation transistor and a first electrode plate of the compensation capacitor;
• a gate of the compensation transistor is electrically connected to the compensation and refreshing sequence signal terminal, and a second electrode of the compensation transistor is electrically connected to the anode node;
• a second electrode plate of the compensation capacitor is electrically connected to the initialization reset voltage terminal.