Method and system for registering circuit design layout and scanning electron microscope image, circuit design layout and imaging error calculation method thereof, and electronic device

A system for registering a circuit design layout and a scanning electron microscope image, comprising:

• an input module, configured to input a circuit design layout to be registered and a scanning electron microscope image to be registered;
• wherein the circuit design layout to be registered comprises at least one design pattern, and the scanning electron microscope image to be registered comprises at least one scanning pattern corresponding to the at least one design pattern;
• a binary processing module, configured to binarize the circuit design layout to be registered to obtain a binary image of the circuit design layout and binarize the scanning electron microscope image to be registered to obtain a binary of the scanning electron microscope image to be registered, wherein in the binary image of the circuit design layout to be registered, a gray value of the design pattern is 1, and a gray value outside the design pattern is 0;
• in the binary image of the scanning electron microscope image to be registered, a gray value of the scanning pattern is 1, and a gray value outside the scanning pattern is 0;
• a Gaussian filtering module, configured to Gaussian filter the binary image of the circuit design layout and the binary image of the scanning electron microscope image to make a gray value to be the largest at central axes of areas where the design pattern and the scanning pattern are located, and
• a registering module, configured to register the circuit design layout and the scanning electron microscope image according to the central axes.