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US 2022/0092736 A1Published application
Video upsampling using one or more neural networks
AssigneeNVIDIA Corporation
InventorsShiqiu Liu, Matthieu Le, Andrew Tao
Life of this patent
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Abstract
Apparatuses, systems, and techniques to enhance video are disclosed. In at least one embodiment, one or more neural networks are used to create a higher resolution video using upsampled frames from a lower resolution video.
Claims36
A system-on-chip (SOC), comprising:
- a graphics core comprising:
- an instruction cache;
- a cache/shared memory;
- floating point logic units to perform 16-bit, 32-bit, or 64-bit floating point operations;
- integer logic units;
- and
- matrix processing units (MPUs) to perform half-precision floating point or 8-bit integer operations;
- memory;
- and
- a system to upsample a lower-resolution frame, blend the upsampled frame with data from a previous frame, upsample the lower-resolution frame using a neural network to infer an upsampled output frame, and blend the upsampled output frame with data from a previous frame.
7 more elements
A processor, comprising:
- a graphics core comprising:
- an instruction cache;
- a cache/shared memory;
- floating point logic units to perform 16-bit, 32-bit, or 64-bit floating point operations;
- integer logic units;
- and
- matrix processing units (MPUs) to perform half-precision floating point and 8-bit integer operations;
- memory;
- and
- wherein the processor is to upsample a lower-resolution frame, blend the upsampled frame with data from a previous frame, upsample the lower-resolution frame using a neural network to infer an upsampled output frame, and blend the upsampled output frame with data from a previous frame.
7 more elements
A method, comprising:
- using a system-on-chip (SOC) to upsample a lower-resolution frame, wherein the SOC comprises:
- a graphics core comprising:
- an instruction cache;
- a cache/shared memory;
- floating point logic units to perform 16-bit, 32-bit, or 64-bit floating point operations;
- integer logic units;
- and
- matrix processing units (MPUs) to perform half-precision floating point and 8-bit integer operations;
- and
- memory;
- and
- blending, by the SOC, the upsampled frame with data from a previous frame;
- upsampling, by the SOC, another lower-resolution frame using a neural network to infer an upsampled output frame;
- and
- blending, by the SOC, the upsampled output frame with data from another previous frame.
12 more elements
Dependencies are inferred from the claim text.