Image processing apparatus
AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
InventorsRyuji Hada, Atsushi Masuda
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Abstract
An image processing apparatus in an embodiment includes a FIFO memory, a plurality of line buffers, an image processing circuit, and a control circuit. The plurality of line buffers store data inputted from a plurality of cameras. The image processing circuit performs predetermined image processing on the data stored in the plurality of line buffers. The control circuit performs control, according to an output control signal, such that output of data to the plurality of line buffers is stopped and the data stopped from being outputted is stored in the FIFO memory.
Claims10
An image processing apparatus comprising:
- a FIFO memory;
- a plurality of line buffers that store data inputted from a plurality of cameras;
- an image processing circuit that performs predetermined image processing on the data stored in the plurality of line buffers;
- and
- a control circuit that performs control, according to an output control signal, such that output of the data to the plurality of line buffers is stopped and the data stopped from being outputted is stored in the FIFO memory.
Dependencies are inferred from the claim text.