Area-Efficient Convolutional Block

A circuit for implementing a convolutional layer of a neural network, the convolutional layer applying a plurality of channel weights to a set of input activations to generate a plurality of layer outputs, comprising:

• a channel selector circuit configured to select a subset of the plurality of channel weights as current channel weights for each clock cycle of a plurality of clock cycles;
• a set of convolutional blocks configured to receive the current channel weights and apply the current channel weights to a set of input activations and generate a current channel output for the current channel weights;
• and
• a channel buffer configured to store the current channel output as a subset of the plurality of layer outputs and output the set of layer outputs after the plurality of clock cycles.

A method for implementing parameters for a convolutional layer of a neural network in a hardware accelerator, comprising:

• identifying parameters of a convolutional layer of the neural network, the parameters including a plurality of weights, and a bias to be added to an accumulated result of the plurality of weights multiplied by a respective plurality of inputs;
• and
• modifying the parameters of the convolutional layer based on characteristics of one or more circuits on which the convolutional layer will be executed by:
• increasing the bias based on a number of the plurality of weights having a negative value;
• or
• encoding the plurality of weights to represent a magnitude of the weights relative to a maximum multiplication performable by the one or more circuits.

A system for determining hardware parameters for implementing a convolutional layer of a neural network in a hardware accelerator, the system including one or more processing elements configured for:

• receiving trained parameters of the convolutional layer of the neural network, the trained parameters comprising a plurality of weights to be multiplied by a respective plurality of inputs and accumulated;
• and
• determining the hardware parameters for implementing the convolutional layer on a hardware accelerator, by:
• determining a value to be added by the hardware accelerator after accumulating multiplication results based on a number of the plurality of weights having a negative value;
• or
• encoding the plurality of weights to represent a magnitude of the plurality of weights relative to a maximum multiplication performable by the hardware accelerator.