Method and Apparatus for Offloading Tasks to Accelerator for Enhancing System Performance Using Configurable Devices

A method for processing data via a dedicated neural network processor, comprising:

• obtaining a trained model file for a machine learning operation;
• extracting model information from the trained model file and storing the model information in an onboard first nonvolatile memory (“NVM”) in a field programmable gate arrays (“FPGA”);
• parsing coefficients representing model layer weights and bias from the trained model and storing the coefficients in a second NVM in the FPGA;
• and
• configuring a portion of the FPGA to be a machine learning processor capable of processing computational operations offloaded from a microcontroller (“MCU”).

A semiconductor device able to be selectively programmed for parallel processing logic operations, comprising:

• an input memory for buffering input signals from an external component;
• a microcontroller (“MCU”) configured to provide a stream of pre-processed data in accordance with the input signals;
• and
• a first portion of configurable logic blocks (“LBs”) of a field programmable gate arrays (“FPGA”), coupled to the MCU, configured to be programmed to behave as a machine learning processor containing a memory controller, wherein the memory controller includes a local memory to cache a portion of coefficients obtained from a dynamic random-access memory (“DRAM”).