Endpoint path margin based integrated circuit design using sub-critical timing paths
AssigneeSynopsys, Inc.
InventorsDeyuan GUO, Kailash PAWAR
Life of this patent
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Abstract
Techniques for integrated circuit (IC) design are disclosed. A path margin is determined for an endpoint of a plurality of timing paths for an IC design. This includes identifying a sub-critical path, among the plurality of timing paths, where the sub-critical path has more slack than a critical path relating to the endpoint. The path margin is generated based on a first slack associated with the sub-critical path. A second slack, relating to at least one of the plurality of timing paths, is modified from a first value to a second value, based on the path margin. A design metric relating to the IC design is updated based on the modified second slack. The IC design is configured to be used to fabricate an IC.
Claims20
A method comprising:
- determining a path margin for an endpoint of a plurality of timing paths for an integrated circuit (IC) design, comprising:
- identifying a sub-critical path, among the plurality of timing paths, wherein the sub-critical path comprises more slack than a critical path relating to the endpoint, and wherein the critical path is the slowest path, among the plurality of timing paths, for the endpoint;
- and
- generating the path margin based on a first slack associated with the sub-critical path;
- modifying a second slack relating to at least one of the plurality of timing paths, from a first value to a second value, based on the path margin;
- and
- updating a design metric relating to the IC design based on the modified second slack, wherein the IC design is configured to be used to fabricate an IC.
A system comprising:
- a processor;
- and
- a memory storing instructions, which when executed by the processor, cause the processor to perform operations comprising:
- determining a path margin for an endpoint of a plurality of timing paths for an integrated circuit (IC) design, comprising:
- generating the path margin based on a first slack associated with a path of the plurality of timing paths;
- modifying a plurality of slacks relating to each of the plurality of timing paths based on the path margin;
- and
- updating a design metric relating to the IC design based on at least one of the modified plurality of slacks, wherein the IC design is configured to be used to fabricate an IC.
A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to perform operations comprising:
- determining a path margin for an endpoint of a plurality of timing paths for an integrated circuit (IC) design, comprising:
- determining that a first slack associated with a first timing path, among the plurality of timing paths, is negative;
- and
- generating the path margin based on the first slack;
- modifying a second slack relating to at least one of the plurality of timing paths, from a first value to a second value, based on the path margin;
- and
- updating a design metric relating to the IC design based on the modified second slack, wherein the IC design is configured to be used to fabricate an IC.
Dependencies are inferred from the claim text.