Memory sub-system with multiple ports having single root virtualization

A method comprising:

• detecting a first host system connected to a first interface port of a plurality of interface ports of a memory device;
• detecting a second host system connected to a second interface port of the plurality of interface ports of the memory device;
• allocating a first range of logical block addresses (LBA) of the memory device to one or more virtual functions (VFs) assigned to the first host system;
• and
• allocating a second range of LBAs of the memory device to one or more VFs assigned to the second host system, wherein the first host system is to access the first range of LBA of the memory device concurrently with the second host system accessing the second range of LBA of the memory device, and wherein the first range of LBAs is different than the second range of LBAs.

A non-transitory computer readable medium comprising instructions, which when executed by a processing device cause the processing device to perform operations comprising:

• detecting a first host system connected to a first interface port of a plurality of interface ports of a memory device;
• detecting a second host system connected to a second interface port of the plurality of interface ports of the memory device;
• allocating a first range of logical block addresses (LBA) of the memory device to one or more virtual functions (VFs) assigned to the first host system;
• and
• allocating a second range of LBAs of the memory device to one or more VFs assigned to the second host system, wherein the first host system is to access the first range of LBA of the memory device concurrently with the second host system accessing the second range of LBA of the memory device, and wherein the first range of LBAs is different than the second range of LBAs.