Systems and methods for optimizing clock distribution in nvme storage enclosures

A method of assembling an NVMe-based information handling system, comprising:

• operatively coupling a processor on a link controller card (LCC) with a data port having network connectivity, the LCC including:
• a PCIe switch communicatively coupled to the processor to receive signals from the processor and to transmit those signals to a plurality of NVMe storage devices operatively coupled to a drive mid-plane baseboard;
• a source clock communicatively coupled to the PCIe switch;
• and
• a connector communicatively coupled to the PCIe switch to relay signals to the plurality of NVMe storage devices at the drive mid-plane baseboard;
• coupling the plurality of NVMe storage devices to the drive mid-plane baseboard, the drive mid-plane baseboard including:
• a clock distribution board communicatively coupled to the source clock via the connector;
• and
• a clock distribution module coupled to the clock distribution board to receive a source clock signal from the source clock, the clock distribution module to distribute clocking signals to the plurality of NVMe storage devices.

A non-volatile memory express (NVMe) based storage system, comprising:

• a storage access module including a processor and an input/output (I/O) port;
• a drive interface board including:
• a first electronic oscillator communicatively coupled to the processor;
• a PCIe switch communicatively coupled to the first electronic oscillator to receive a clock signal from the first electronic oscillator;
• a connector communicatively coupled to the electronic oscillator to relay clock signals to a plurality of clock distribution modules at a drive mid-plane baseboard and the connector communicatively coupled to the PCIe switch to relay data signals between the processor and a plurality of NVMe storage devices at the drive mid-plane baseboard;
• a cooling system including a plurality of fans placed between the drive interface board and the drive mid-plane baseboard;
• a connection board operatively coupling the drive interface board to the connector at the drive mid-plane baseboard;
• wherein the drive mid-plane baseboard is communicatively coupled to the electronic oscillator, the drive mid-plane baseboard including:
• data and power connection to the plurality of NVMe storage devices;
• and
• each of the plurality of clock distribution modules to relay clock signals to a group of the NVMe storage devices.