Memory system and method
AssigneeKioxia Corporation
InventorKenta YASUFUKU
Life of this patent
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Abstract
According to an embodiment, a memory system includes a controller which includes an interface connectable with a host with cache coherency kept. The controller is configured to: before the host writes a command to an I/O submission queue, read the I/O submission queue; after the reading, detect via the interface an invalidation request, the invalidation request being based on writing of the command by the host to the I/O submission queue; and in response to the invalidation request, acquire the command in the I/O submission queue.
Claims20
A memory system comprising:
- a controller including an interface connectable with a host with cache coherency kept, the controller being configured to:
- before the host writes a command to an I/O submission queue, read the I/O submission queue;
- after the reading, detect via the interface an invalidation request, the invalidation request being based on writing of the command by the host to the I/O submission queue;
- and
- in response to the invalidation request, acquire the command in the I/O submission queue.
A method of controlling a memory system connectable with a host, the method comprising:
- connecting to the host with cache coherency kept;
- before the host writes a command to an I/O submission queue, reading the I/O submission queue;
- after the reading, detecting an invalidation request, the invalidation request being based on writing of the command by the host to the I/O submission queue;
- and
- in response to the invalidation request, acquiring the command written to the I/O submission queue.
Dependencies are inferred from the claim text.