US 2022/0091992 A1Published application

Device, system and method to provide line level tagging of data at a processor cache

AssigneeIntel Corporation

InventorsVedvyas Shanbhogue, Siddhartha Chhabra

Life of this patent

Estimating the term…

Loading patent…

Abstract

Techniques and mechanisms for identifying tag information that describes data to be cached at a processor. In an embodiment, a memory controller services a memory access request from the processor, wherein the memory controller reads multiple chunks of data from a memory device, and determines first tag information which corresponds to the multiple chunks. One or more of the multiple chunks are sent to the processor in a response to the request. Based on the first tag information, the memory controller detects for a match—if any—between at least two tags. Where such a match is detected, the memory controller further indicates to the processor that second tag information corresponds to the one or more chunks. In another embodiment, the first tag information is more granular than the second tag information.

Claims20

Dependent claims

A memory controller comprising:

protocol circuitry to receive a request from a processor and, based on the request, to read data from an addressable location of a memory device, wherein the data comprises multiple chunks, and wherein the protocol circuitry is further to send one or more chunks of the multiple chunks to the processor in a response to the request;
tag identification circuitry, coupled to the protocol circuitry, to determine first tag information which corresponds to the data, wherein the first tag information provides a first granularity at which the multiple chunks each correspond to a respective tag;
and
tag evaluation circuitry, coupled to the tag identification circuitry, to detect a match between at least two tags based on the first tag information;
wherein, based on the match, the protocol circuitry is to indicate to the processor that second tag information corresponds to the one or more chunks, wherein the second tag information provides a second granularity at which the one or more chunks each correspond to a respective tag, wherein the first granularity is more than the second granularity.

2 more elements

A system comprising:

a processor;
a memory device;
a memory controller coupled to the processor and the memory device, the memory controller comprising:
protocol circuitry to receive a request from the processor and, based on the request, to read data from an addressable location of the memory device, wherein the data comprises multiple chunks, and wherein the protocol circuitry is further to send one or more chunks of the multiple chunks to the processor in a response to the request;
tag identification circuitry, coupled to the protocol circuitry, to determine first tag information which corresponds to the data, wherein the first tag information provides a first granularity at which the multiple chunks each correspond to a respective tag;
and
tag evaluation circuitry, coupled to the tag identification circuitry, to detect a match between at least two tags based on the first tag information;
wherein, based on the match, the protocol circuitry is to indicate to the processor that second tag information corresponds to the one or more chunks, wherein the second tag information provides a second granularity at which the one or more chunks each correspond to a respective tag, wherein the first granularity is more than the second granularity;
and
a display device coupled to the processor, the display device to display an image based on the one or more chunks.

7 more elements

Dependencies are inferred from the claim text.