Memory-aware pre-fetching and cache bypassing systems and methods

A tangible, non-transitory, computer-readable medium storing instructions executable by control circuitry of a computing system, wherein the instructions comprise instructions to:

• receive, by the control circuitry, a write memory access request from a processing sub-system for storing a data block at a demanded storage location in a memory array;
• determine, by the control circuitry, whether a cache bypassing associated with a cache, a pre-fetch buffer, or both, of the computing system is enabled;
• instruct, by the control circuitry, the memory array to store the data block at the demanded storage location in response to determining that the cache bypassing is enabled;
• and
• instruct, by the control circuitry, the cache, the pre-fetch buffer, or both, to store a copy of the data block in response to determining that the cache bypassing is disabled.

A method comprising:

• receiving, by a memory controller of a memory system comprising a memory array and a memory cache, a pre-fetch buffer, or both, a memory access request targeting a memory page of the memory array via a memory bus;
• determining, by the memory controller, whether a data block of the memory page is stored in the memory cache, the pre-fetch buffer, or both;
• determining, by the memory controller, whether a cache bypassing associated with the memory cache, the pre-fetch buffer, or both is enabled in response to determining that the data block of the memory page is not stored in the memory cache, the pre-fetch buffer, or both, wherein the cache bypassing is indicative of a statistical likelihood that a subsequent memory access request will target the memory page, wherein the cache bypassing is determined based on one or more previously determined counter values each indicating a number of consecutive memory access requests previously targeting the memory page;
• and
• instructing, by the memory controller, the memory array to output the data block of the memory page directly to a processor-side via a memory bus in response to determining that the cache bypassing is enabled.