System, apparatus and method for user space object coherency in a processor

At least one computer readable storage medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

• receiving, in a compiler, a code sequence;
• identifying, in the compiler, one or more read objects in the code sequence, and inserting, for each of the one or more read objects, a map add instruction into the code sequence, the map add instruction to cause a processor to write an entry into a map table for a corresponding one of the one or more read objects;
• inserting a map lock instruction into the code sequence following one or more data manipulation instructions of the code sequence, the map lock instruction to cause the processor to lock the map table with respect to the code sequence and verify whether any of the one or more read objects were modified during execution of the code sequence outside of the code sequence;
• and
• compiling the code sequence into a compiled code sequence and storing the compiled code sequence in a storage, the compiled code sequence to enable the processor to provide hardware support of multi-object coherency atomic transactional operation transparently to a programmer of the code sequence.

A system comprising:

• a processor comprising:
• a first core having a first execution circuit to execute instructions, a first cache memory coupled to the first execution circuit, and a first table storage element to store a first plurality of entries each to store object metadata of an object used in a code sequence, the object metadata including a user space address of the object, wherein in response to a map add instruction of an instruction set architecture, the first table storage element is to store a user space address of a first object and a version number of the first object in a first entry of the first table storage element;
• a second core having a second execution circuit to execute instructions, a second cache memory coupled to the second execution circuit, and a second table storage element to store a second plurality of entries each to store object metadata of an object used in another code sequence;
• and
• a coherency circuit coupled to the first core and the second core, wherein in response to eviction of the first entry from the first table storage element, the coherency circuit is to send an invalidation message to the second table storage element to cause the second table storage element to update a status of an entry associated with the first object in the second table storage element to a fail state;
• and
• a system memory coupled to the processor.