Unified Memory Management for a Multiple Processor System

A multi-processor unified memory management system, comprising:

• a first programmable processor system that communicates via an inter-chip link with a second programmable processor system, wherein the first programmable processor system comprises:
• a first inter-chip memory management module configured to:
• analyze memory access transactions;
• translate outbound memory-mapped transactions into non-memory mapped transactions comprising coded memory address data;
• and
• translate inbound non-memory mapped transactions into memory-mapped transactions based on coded memory address data;
• and
• the second programmable processor system that communicates via the inter-chip link with the first programmable processor system, wherein the second programmable processor system comprises:
• a second inter-chip memory management module configured to:
• analyze memory access transactions;
• translate outbound memory-mapped transactions into non-memory mapped transactions comprising coded memory address data;
• and
• translate inbound non-memory mapped transactions into memory-mapped transactions based on coded memory address data.