Adaptive device data correction with increased memory failure handling
AssigneeIntel Corporation
InventorsLei CHEN, Liyang LING, Xiaodong QIU, Yong JIANG
Life of this patent
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Abstract
An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to identify failed memory regions in a memory by a rank, bank, and device associated with the failed memory region, and provide recovery for failed memory regions in three or more banks of a first rank of the memory or three or more devices of the first rank of the memory by virtual lock step device data correction with one or more other ranks of the memory. Other embodiments are disclosed and claimed.
Claims20
An electronic apparatus, comprising:
- one or more substrates;
- and
- a controller coupled to the one or more substrates, the controller including circuitry to:
- identify failed memory regions in a memory by a rank, bank, and device associated with the failed memory region, and
- provide recovery for failed memory regions in three or more banks of a first rank of the memory or three or more devices of the first rank of the memory by virtual lock step device data correction with one or more other ranks of the memory.
An electronic system, comprising:
- memory organized as two or more ranks, where each rank is organized as two or more banks and two or more devices;
- and
- a controller communicatively coupled to the memory, the controller including circuitry to:
- identify failed memory regions in the memory by a rank, bank, and device associated with the failed memory region, and
- provide recovery for failed memory regions in three or more banks of a first rank of the memory or three or more devices of the first rank of the memory by virtual lock step device data correction with one or more other ranks of the memory.
A method, comprising:
- identifying failed memory regions in a memory by a rank, bank, and device associated with the failed memory region;
- and
- providing recovery for failed memory regions in three or more banks of a first rank of the memory or three or more devices of the first rank of the memory by virtual lock step device data correction with one or more other ranks of the memory.
Dependencies are inferred from the claim text.