Field programmable gate array (fpga) with automatic error detection and correction function for programmable logic modules

A field programmable gate array (FPGA) with an automatic error detection and correction function for programmable logic modules, comprising a programmable logic module and an error checking and correction device, wherein

• the programmable logic module comprises a plurality of programmable logic registers, and each programmable logic register of the plurality of programmable logic registers refreshes and writes obtained input data according to a clock signal;
• the error checking and correction device comprises a check code generation circuit, M check code registers, a check circuit, a decoding circuit, and a trigger circuit;
• N input terminals of the check code generation circuit are respectively connected to corresponding input terminals of N programmable logic registers to obtain N pieces of input data;
• M output terminals of the check code generation circuit are respectively connected to the M check code registers;
• the check code generation circuit performs error correcting code (ECC) encoding on the N pieces of input data to generate M check codes, and each check code register of the M check code registers refreshes and writes a corresponding check code according to a clock signal of programmable logic registers corresponding to the error checking and correction device;
• output terminals of the N programmable logic registers and output terminals of the M check code registers are all connected to input terminals of the check circuit;
• output terminals of the check circuit are connected to input terminals of the decoding circuit to provide syndromes, and the syndromes are used for indicating that a fault register with a data error exists in the N+M registers;
• and
• the trigger circuit is connected to an enable terminal of the decoding circuit;
• the decoding circuit generates N+M upset signals that have a predetermined pulse width and correspond to the syndromes according to trigger enable pulses of the trigger circuit, and respectively outputs the N+M upset signals to the N programmable logic registers and the M check code registers to control the fault register to directly and asynchronously upset content to correct the data error.