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US 2022/0091928 A1Published application
Infrastructure integrity checking
AssigneeTexas Instruments Incorporated
InventorsDesmond FERNANDES, Indu PRATHAPAN, Jasbir SINGH, Prathap SRINIVASAN, Rishav KARKI
Life of this patent
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Abstract
A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.
Claims23
A device, comprising:
- a first component having a data input and a data output including a first line and a second line;
- an error correction code (ECC) generation circuit having an input coupled to the data input of the first component, the ECC generation circuit having an output;
- a second component having a data input coupled to the output of the ECC generation circuit, the second component having a data output;
- an ECC error detection circuit having a first data input including a first line and a second line, wherein the first line of the first data input of the ECC error detection circuit is coupled to the first line of the data output of the first component, and wherein the ECC error detection circuit further includes a second data input coupled to the data output of the second component;
- and
- a logic gate including a first input coupled to the second line of the data output of the first component,
- wherein the logic gate further includes an output coupled to the second line of the first data input of the ECC error detection circuit.
4 more elements
A device, comprising:
- a first component having a data input, a control output, and a data output;
- an error correction code (ECC) generation circuit having an input coupled to the data input of the first component, the ECC generation circuit having an output;
- a second component having a data input, a control output, and a data output, the data input of the second component is coupled to the output of the ECC generation circuit;
- a control signal comparator circuit having a first control input coupled to the control output of the first component, a second control input coupled to the control output of the second component, a data input coupled to the data output of the first component, and a data output;
- and
- an ECC error detection circuit having a first data input coupled to the data output of the control signal comparator circuit, and the ECC error detection circuit including a second data input coupled to the data output of the second component.
3 more elements
A system-on-chip (SoC), comprising:
- a first component having a data input and a data output, the first component configured to perform at least one of bus width conversion, address decoding, arbitration, bus protocol conversion, or burst splitting;
- an error correction code (ECC) generation circuit having an input coupled to the data input of the first component, the ECC generation circuit having an output;
- a second component having a data input coupled to the output of the ECC generation circuit, the second component having a data output, the second component configured to perform the function;
- and
- an ECC error detection circuit having a first data input coupled to the data output of the first component, and the ECC error detection circuit including a second data input coupled to the data output of the second component.
2 more elements
(canceled)
A device, comprising:
- a first component including a data input and a data output;
- an error correction code (ECC) generation circuit including an input coupled to the data input of the first component, wherein the ECC generation circuit further includes an output, wherein the ECC generation circuit is configured to generate ECC words based on data received on the input of the ECC generation circuit and provide the ECC words on the output of the ECC generation circuit, and wherein the ECC words generated by the ECC generation circuit comprise a first set of ECC bits;
- a second component including a data input coupled to the output of the ECC generation circuit, wherein the second component further includes a data output;
- and
- an ECC error detection circuit including a first data input coupled to the data output of the first component,
- wherein the ECC error detection circuit further includes a second data input coupled to the data output of the second component, and
- wherein the ECC error detection circuit is configured to calculate a second set of ECC bits based on data on the data output of the first component and to compare the second set of ECC bits to the first set of ECC bits contained in the ECC words provided on the output of the ECC generation circuit.
4 more elements
A device, comprising:
- a first component including a data input and a data output, wherein the first component comprises first circuitry;
- an error correction code (ECC) generation circuit including an input coupled to the data input of the first component, wherein the ECC generation circuit further includes an output;
- a second component including a data input coupled to the output of the ECC generation circuit, wherein the second component further includes a data output, wherein the second component comprises second circuitry, and wherein the second circuitry comprises a same instance of the first circuitry;
- and
- an ECC error detection circuit including a first data input coupled to the data output of the first component,
- wherein the ECC error detection circuit further includes a second data input coupled to the data output of the second component.
3 more elements
Dependencies are inferred from the claim text.