Methods and apparatus to determine execution cost
AssigneeIntel Corporation
InventorsNiranjan Hasabnis, Justin Gottschlich, Jesmin Jahan Tithi, Anand Venkat
Life of this patent
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Abstract
Methods, apparatus, systems, and articles of manufacture to determine execution cost are disclosed. An example apparatus includes memory; instructions included in the apparatus; and processor circuitry to execute the instruction to: cause a plurality of instructions corresponding to a mnemonic to be executed; determine an average execution cost of the plurality of instructions; determine a standard deviation of execution costs of the plurality of instructions; and generate a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.
Claims35
An apparatus to generate a mapping table based on execution cost, the apparatus comprising:
- memory;
- instructions included in the apparatus;
- and
- processor circuitry to execute the instructions to:
- cause a plurality of instructions corresponding to a mnemonic to be executed;
- determine an average execution cost of the plurality of instructions;
- determine a standard deviation of execution costs of the plurality of instructions;
- and
- generate a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.
A non-transitory computer readable medium comprising instructions which, when executed, cause one or more processors to at least:
- cause a plurality of instructions corresponding to a mnemonic to be executed;
- determine an average execution cost of the plurality of instructions;
- determine a standard deviation of execution costs of the plurality of instructions;
- and
- generate a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.
An apparatus to generate a mapping table based on execution cost, the apparatus comprising:
- interface circuitry;
- and
- processor circuitry including one or more of:
- at least one of a central processing unit, a graphic processing unit or a digital signal processor, the at least one of the central processing unit, the graphic processing unit or the digital signal processor having control circuitry, one or more registers, and arithmetic and logic circuitry to perform one or more first operations corresponding to instructions in the apparatus, and;
- a Field Programmable Gate Array (FPGA), the FPGA including logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the logic gate circuitry and interconnections to perform one or more second operations;
- or
- Application Specific Integrate Circuitry (ASIC) including logic gate circuitry to perform one or more third operations;
- the processor circuitry to perform at least one of the first operations, the second operations or the third operations to instantiate:
- cost mapping circuitry to:
- cause a plurality of instructions corresponding to a mnemonic to be executed;
- determine an average execution cost of the plurality of instructions;
- determine a standard deviation of execution costs of the plurality of instructions;
- and
- generate a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.
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A method to generate a mapping table based on execution cost, the method comprising:
- causing a plurality of instructions corresponding to a mnemonic to be executed;
- determining, by executing an instruction with one or more processors, an average execution cost of the plurality of instructions;
- determining, by executing an instruction with the one or more processors, a standard deviation of execution costs of the plurality of instructions;
- and
- generating, by executing an instruction with the one or more processors, a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.
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Dependencies are inferred from the claim text.