Information processing device and processing method
AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
InventorsMikio HASHIMOTO, Masami AIZAWA, Satoru SUZUKI, Tsuneki SASAKI
Life of this patent
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Abstract
According to one embodiment, an information processing device includes a processor, a controller, and a memory. The memory stores a vector address related to an interrupt request executed on condition that the processor is in a sleep state. The controller receives the interrupt request and detects that the processor transitions to the sleep state, detects fetch of the vector address of the interrupt request after the sleep state of the processor is detected, and inputs the vector address that is related to the interrupt request and stored in the memory into the processor in a case where the fetch of the vector address of the interrupt request is detected.
Claims20
An information processing device comprising:
- a processor;
- a controller;
- and
- a memory, wherein
- the memory stores a vector address related to an interrupt request executed on condition that the processor is in a sleep state, and
- the controller:
- receives the interrupt request and detects that the processor transitions to the sleep state;
- detects fetch of the vector address of the interrupt request after the sleep state of the processor is detected;
- and
- inputs the vector address related to the interrupt request and stored in the memory into the processor in a case where the fetch of the vector address of the interrupt request is detected.
A processing method executed by an information processing device including a processor, a controller, and a memory that stores a vector address related to an interrupt request executed on condition that the processor is in a sleep state, the method comprising:
- receiving the interrupt request and detecting that the processor transitions to the sleep state;
- detecting fetch of the vector address of the interrupt request after detecting the sleep state of the processor;
- and
- inputting the vector address related to the interrupt request and stored in the memory into the processor in a case where the fetch of the vector address of the interrupt request is detected.
Dependencies are inferred from the claim text.