Instruction Set Architecture and Microarchitecture for Early Pipeline Re-steering Using Load Address Prediction to Mitigate Branch Misprediction Penalties

One or more non-transitory computer-readable media comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to:

• decode a load instruction, at decode circuitry, wherein the load instruction includes a first indication of whether a branch operation, dependent on a load operation of the load instruction, is a candidate for prediction;
• issue, at Load Address Predictor (LAP) circuitry, a load prefetch request to memory for data for the load operation based on the first indication indicative of the branch operation being a candidate for prediction;
• execute, at compute circuitry, an outcome for the branch operation based on the data from the load prefetch request;
• and
• transmit a signal, at re-steering circuitry, to cause flushing of data associated with the load instruction in response to a mismatch between the outcome for the branch operation and a stored prediction value for the branch.