Systems and methods to load a tile register pair

A chip comprising:

• a plurality of memory controllers;
• a level-two (L2) cache memory coupled to the plurality of memory controllers;
• a processor coupled to the plurality of memory controllers, and coupled to the L2 cache memory, the processor having a plurality of cores, including a core to perform operations corresponding to an instruction identifying a first two-dimensional source tile in memory and a second two-dimensional source tile in the memory, including to:
• determine that an indicator indicates that a pair of matrices are to be loaded;
• and
• load elements from element positions of each row of the first two-dimensional source tile into corresponding element positions of a first two-dimensional destination tile, and load elements from element positions of each row of the second two-dimensional source tile into corresponding element positions of a second two-dimensional destination tile, in response to the determination that the indicator indicates that the pair of matrices are to be loaded;
• an interconnect coupled to the processor;
• and
• a bus controller coupled to the processor.

A chip comprising:

• a plurality of memory controllers;
• a level-two (L2) cache memory coupled to the plurality of memory controllers;
• a processor coupled to the plurality of memory controllers, and coupled to the L2 cache memory, the processor having a plurality of heterogeneous graphics cores, including a heterogeneous graphics core to perform operations corresponding to an instruction identifying a first two-dimensional source tile in memory and a second two-dimensional source tile in the memory, including to:
• determine that an indicator indicates that a pair of matrices are to be loaded;
• and
• load elements from element positions of each of eight rows of the first two-dimensional source tile into corresponding element positions of a first two-dimensional destination tile, and load elements from element positions of each of eight rows of the second two-dimensional source tile into corresponding element positions of a second two-dimensional destination tile, in response to the determination that the indicator indicates that the pair of matrices are to be loaded, wherein the first and second two-dimensional destination tiles each comprise a plurality of registers of the processor;
• an interconnect coupled to the processor;
• and
• a bus controller coupled to the processor.

A method performed by a chip, the method comprising:

• accessing memory with a plurality of memory controllers of the chip;
• storing data in a level-two (L2) cache memory of the chip;
• processing data with a plurality of cores of a processor of the chip;
• performing operations corresponding to an instruction with a core of the plurality of cores, the instruction identifying a first two-dimensional source tile in the memory and a second two-dimensional source tile in the memory, wherein the operations include:
• determining that an indicator indicates that a pair of matrices are to be loaded;
• and
• loading elements from element positions of each row of the first two-dimensional source tile into corresponding element positions of a first two-dimensional destination tile, and loading elements from element positions of each row of the second two-dimensional source tile into corresponding element positions of a second two-dimensional destination tile, in response to the determination that the indicator indicates that the pair of matrices are to be loaded;
• transmitting data from the processor to an interconnect of the chip;
• and
• accessing a bus with a bus controller of the chip.

A computer system comprising:

• a system memory;
• and
• a plurality of memory controllers coupled with the system memory;
• a level-two (L2) cache memory coupled to the plurality of memory controllers;
• a processor coupled to the plurality of memory controllers, and coupled to the L2 cache memory, the processor having a plurality of cores, including a core to perform operations corresponding to an instruction identifying a first two-dimensional source tile in memory and a second two-dimensional source tile in the memory, including to:
• determine that an indicator indicates that a pair of matrices are to be loaded;
• and
• load elements from element positions of each row of the first two-dimensional source tile into corresponding element positions of a first two-dimensional destination tile, and load elements from element positions of each row of the second two-dimensional source tile into corresponding element positions of a second two-dimensional destination tile, in response to the determination that the indicator indicates that the pair of matrices are to be loaded;
• an interconnect coupled to the processor;
• and
• a bus controller coupled to the processor.