Refresh management list for dram
AssigneeAdvanced Micro Devices, Inc.
InventorKevin M. Brandl
Life of this patent
Estimating the term…
Abstract
A memory controller includes a command queue having a first input for receiving memory access requests, and a memory interface queue having an output for coupling to a memory channel adapted for connecting to at least one dynamic random access memory (DRAM) module. A refresh control circuit monitors activate commands to be sent over the memory channel. In response to an activate command meeting a designated condition, the refresh control circuit identifies a candidate aggressor row associated with the activate command. A command is sent to the DRAM requesting that the candidate aggressor row be queued for mitigation in a future refresh or refresh management event.
Claims26
A memory controller, comprising:
- a command queue having a first input for receiving memory access requests;
- a memory interface queue having an output for coupling to a memory channel adapted for coupling to a dynamic random access memory (DRAM);
- an arbiter coupled to the command queue for selecting entries from the command queue, and placing them in the memory interface queue causing them to be transmitted over the memory channel;
- and
- a refresh control circuit coupled to the arbiter and operable to:
- monitor activate commands to be sent over the memory channel;
- in response to an activate command meeting a designated condition, identify a candidate aggressor row associated with the activate command;
- and
- transmit a command to the DRAM requesting that the candidate aggressor row be queued for mitigation in a future refresh or refresh management event.
A data processing system, comprising:
- a data processor;
- a data fabric coupled to the data processor;
- and
- a memory controller coupled to the data fabric for fulfilling memory requests from the data processor, the memory controller comprising:
- an output for coupling to a memory channel adapted for coupling to at least one dynamic random access memory (DRAM);
- and
- a refresh control circuit, wherein the
- refresh control circuit is operable to:
- monitor activate commands to be sent over the memory channel;
- in response to an activate command meeting a designated condition, identify a candidate aggressor row associated with the activate command;
- and
- transmit a command to the DRAM requesting that the candidate aggressor row be queued for mitigation in a future refresh or refresh management event.
A method, comprising:
- receiving a plurality of memory access requests including memory reads and memory writes;
- selectively placing memory access commands for fulfilling the memory access requests in a memory interface queue and transmitting the memory access commands from the memory interface queue to a memory channel coupled to at least one dynamic random access memory (DRAM);
- monitoring activate commands to be sent over the memory channel;
- in response to an activate command meeting a designated condition, identifying a candidate aggressor row associated with the activate command;
- and
- transmitting a command to the DRAM requesting that the candidate aggressor row be queued for mitigation in a future refresh or refresh management event.
Dependencies are inferred from the claim text.