Memory access method and intelligent processing apparatus

An intelligent processing apparatus, comprising:

• a processor, generating a read command to read data from a memory;
• and
• a direct access memory (DMA) controller, reading data from the memory according to the read command, the DMA controller comprising:
• a configuration circuit, providing a first configuration parameter according to a first operation mode;
• a signal port, receiving the read command;
• an address generation circuit, generating a plurality of first address signals to the memory according to the first configuration parameter and the read command;
• a data processing circuit, receiving data that the memory outputs in response to the first address signals, and performing a data interception process on the data received from the memory according to the read command and the first configuration parameter;
• and
• a data port, transmitting the data processed by the data processing circuit to the processor;
• wherein, the first address signals comprise a plurality of non-consecutive address signals such that the data read from the memory and processed by the data processing circuit corresponds to n-dimensional data blocks, where n is a positive integer greater than 1.

A memory access method, applied to an intelligent processing apparatus, the intelligent processing apparatus comprising a processor, the memory access method comprising:

• receiving a read command from the processor to read data from a memory;
• providing a first configuration parameter according to a first operation mode;
• generating a plurality of first address signals to the memory according to the first configuration parameter and the read command;
• and
• receiving data that the memory outputs in response to the first address signals, and performing a data interception process on the data received from the memory according to the read command and the first configuration parameter to output to the processor;
• wherein, the first address signals comprise a plurality of non-consecutive address signals such that the data read from the memory and processed by the data processing circuit corresponds to n-dimensional data blocks, where n is a positive integer greater than 1.